Collaborative Research: Algorithms for Simulation and Design of Analog VLSI Lattices

合作研究：模拟 VLSI 晶格的仿真和设计算法

• 批准号: 0913048
• 负责人: Harish Bhat
• 金额: $ 9.55万
• 依托单位: University of California - Merced
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2009
• 资助国家: 美国
• 起止时间: 2009-05-15 至 2011-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0913048&HistoricalAwards=false
• 关键词: Collaborative; Research; Algorithms; Simulation; Design

New technologies in areas such as wireless communication, portable computing, and handheld electronics have increased the demand for signal processing at high frequencies. Part of the challenge in designing silicon integrated circuits that can meet this demand is to overcome limitations in the efficiency and frequency bandwidth of modern transistors. Here it is proposed to use two-dimensional networks of inductors and capacitors to overcome these limitations. These high-speed, high-efficiency networks have a cut-off frequency that is higher than that for silicon-based transistors. Moreover, such networks can be incorporated into standard silicon chips that can be fabricated at low cost. The proposed research has the potential to revolutionize high-frequency analog signal processing, leading to chips that operate up to 1000 times faster than current ones.There are a large number of possible designs for such networks, and only a small number of these possibilities have already been explored. The proposed research seeks to develop algorithms that greatly assist in the simulation and design of two-dimensional inductor-capacitor networks. Simulating a large network involves the solution of a large, coupled system of equations that can be simplified greatly through mathematical analysis. It is proposed to use this simplification to develop fast, scalable algorithms and codes for network simulation. This would enable engineers to quickly learn the effect of changing one or more of the thousands of parameters in a typical large-scale inductor-capacitor network.It is also proposed to use optimization methods to automatically design lattices that achieve prescribed input-output relationships. The optimization work will use as a foundation the prior results of the proposers, including, for example, the development of a two-dimensional network that computes Fourier transforms in the analog domain. Such physically motivated ideas will be coupled with modern tools of parallel numerical computing such as PetSC (the Portable Extensible Toolkit for Scientific Computation) and TAO (the Toolkit for Advanced Optimization). This will result in fast, accurate tools that enable engineers to rapidly optimize the design of a lattice to achieve desired performance specifications.The expertise gained in carrying out the proposed research will enable the investigators to train students and researchers to solve problems in modern computational science and engineering. The proposed research encourages multidisciplinary interaction between scientists, engineers, applied mathematicians, and computer scientists spanning the spectrum from developers to users of computational tools.

无线通信、便携式计算和手持电子等领域的新技术增加了对高频信号处理的需求。设计满足这种需求的硅集成电路的部分挑战是克服现代晶体管在效率和频率带宽方面的限制。本文提出利用电感和电容的二维网络来克服这些限制。这些高速、高效的网络具有比硅基晶体管更高的截止频率。此外，这种网络可以被整合到标准硅芯片中，以低成本制造。这项提议的研究有可能彻底改变高频模拟信号处理，导致芯片的运行速度比目前的芯片快1000倍。这种网络有很多可能的设计，但只有一小部分已经被探索过。提出的研究旨在开发算法，极大地协助二维电感-电容器网络的模拟和设计。模拟一个大型网络需要求解一个大型的、耦合的方程组，而这些方程组可以通过数学分析大大简化。提出利用这种简化来开发快速、可扩展的网络仿真算法和代码。这将使工程师能够快速了解在典型的大型电感-电容器网络中改变数千个参数中的一个或多个参数的影响。提出了利用优化方法自动设计达到规定输入输出关系的网格。优化工作将使用提议者的先前结果作为基础，包括，例如，在模拟域中计算傅里叶变换的二维网络的开发。这种物理动机的想法将与并行数值计算的现代工具相结合，如PetSC（科学计算的便携式可扩展工具包）和TAO（高级优化工具包）。这将产生快速，准确的工具，使工程师能够快速优化晶格的设计，以达到所需的性能规格。在进行拟议的研究中获得的专业知识将使研究人员能够培训学生和研究人员解决现代计算科学和工程中的问题。拟议的研究鼓励科学家、工程师、应用数学家和计算机科学家之间的多学科互动，从开发人员到计算工具的用户。