Small-Scale Dynamic Reconfigurability for Large-Scale Benefits

通用处理器（GPP）被设计为在固定配置上实现，该固定配置平均而言是良好的，但可能不太适合于个别应用。 事实上，应用程序可以具有完全不同的执行特性（例如，分支预测技术偏好、高速缓存配置和策略偏好、低功耗机会）。 这表明使用设备可重构性，但是任何实质规模的通用可重构逻辑（例如，大多数现场可编程门阵列（FPGA）技术）是缓慢的，缺乏密度，并且是耗电的。 然而，许多处理器结构可容易地适应于各种各样的配置。 本研究将发展动态的，小规模的，部分可重构的结构。 这种“Dynaptable”方法的另一个好处是，它集成了架构、逻辑和电路级别的工作。Dynaptable方法包括三个关键要素： 1. 灵活的结构：设计关键的处理器结构，使用合理数量的可重新配置硬件，以低成本、非侵入性的方式提供灵活性。 2. 运行时监控：确定当前配置与其他可能的竞争配置相比的性能或有效性。 3. 动态重新配置：使用运行时监控的结果来适应新的配置，从而提高所选的品质因数（例如性能、能量延迟积、容错）。该研究将确定增加小规模可重配置性的最有利可图的地方，设计必要的可重配置元件，并开发最有效、成本最低的动态监控和适应技术。 这项工作将对各种处理器组件（分支预测器、缓存、数据路径等）的设计产生影响。适用于各种处理环境（嵌入式系统、超标量、SMT等）。 最终目标是开发一种一致的方法，用于动态调整GPP微架构，以提高性能、降低功耗并增加容错能力。

General purpose processors (GPPs) are designed to implement on fixed configuration that is good on average but may not be well suited for individual applications. In fact, applications can have drastically different execution characteristics (e.g. branch prediction technique preference, cache configuration and policy preference, low-power opportunities). This suggests the use of device reconfigurability, but generic reconfigurable logic of any substantial scale (e.g. most field programmable gate array (FPGA) technology) is slow, lacks density, and is power-hungry. Yet many processor structures are easily adaptable to a wide variety of configurations. This research will develop dynamic, small-scale, partial reconfigurability for such structures. This "Dynaptable" approach has the further benefit that it integrates work at the architectural, logic, and circuit levels.The Dynaptable approach consists of three key elements: 1. Flexible structures: designing key processor structures with judicious amounts of reconfigurable hardware to provide flexibility in a low-cost, non-invasive way. 2. Run-time monitoring: determining the current configuration's performance or effectiveness compared to other possible competing configurations. 3. Dynamic reconfiguration: using the results of run-time monitoring to adapt to a new configuration that improves the chosen figure of merit (e.g. performance, energy-delay product, fault tolerance).The research will identify the most profitable places for adding small-scale reconfigurability, design the requisite reconfigurable elements, and develop the most effective and lowest-cost techniques for dynamic monitoring and adaptation. This work will have an impact on the design of a variety of processor components (branch predictor, cache, datapath, etc.) for a range of processing environments (embedded systems, superscalar, SMT, etc.). The final goal is to develop a consistent methodology for dynamically adapting GPP microarchitectures for improved performance, lower power, and increased fault tolerance.