CAREER: Data-flow Analysis in the Memory Management of Real-Time Multimedia Processing Systems
CAREER: Data-flow Analysis in the Memory Management of Real-Time Multimedia Processing Systems
批准号:
0133318
负责人:
Florin Balasa
金额:
$37.5万
依托单位国家:
美国
项目类别:
Continuing Grant
财政年份:
2002
资助国家:
美国
项目状态:
已结题
起止时间:
2002-06-01 至 2007-05-31
中文摘要
本研究的重点是设计基于数据流分析的实时多维信号处理的内存管理新技术。数据流分析是沿着该项目的引导探索机制,与传统的基于调度的调查相比,它允许更多的探索自由,因为内存管理任务通常只需要相对的(而不是精确的)生命周期信息。此外,数据流分析使内存管理任务的研究在所需的粒度级别-整个数组和标量级别之间-权衡计算工作量和解决方案optimality.Part的这个项目研究非标量方法计算内存大小的实时多媒体算法。这项研究解决了新的内存计算的主题:处理一个大类的参数规格,并在高吞吐量的应用程序中处理并行。这个项目还解决了问题,得出一个多层次的存储器架构优化的面积和/或功率,受到性能约束。另一个研究方向是将数据从嵌入式应用程序代码优化映射到片上SRAM或片外DRAM,以最大限度地提高应用程序的整体存储器访问性能。(2)开发了一个计算内存大小的web工具。
英文摘要
This research focuses on devising novel techniques based on data-flow analysis in the memory management of real-time multidimensional signal processing. Data-flow analysis is the steering exploration mechanism along this project, allowing more exploration freedom than the traditional scheduling -based investigation, since the memory management tasks usually need only relative (rather than exact) lifetime information. Moreover, data-flow analysis enables the study of memory management tasks at the desired level of granularity -- between whole array and the scalar level -- trading-off computational effort and solution optimality.Part of this project investigates non-scalar methods for computing the memory size in real-time multimedia algorithms. This research addresses novel memory computation topics: dealing with a large class of parametric specifications, and dealing with parallelism in high-throughput applications. This project addresses also the problem of deriving a multilevel memory architecture optimized for area and/or power, subject to performance constraints. Another research direction is the optimized mapping of data from an embedded application code into the on-chip SRAM or the off-chip DRAM for maximizing the overall memory access performance of the application.The educational component of this research includes (1) the development of a graduate course covering algorithmic aspects of high-level synthesis and system design methodologies; (2) the development of a web tool for memory size computation.
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