SGER: Exploring Massive Chip Level Active Deskewing for VLSI Chips Beyond 20GHz

在过去的几十年中，时钟速率和VLSI芯片的集成度已经达到了一个水平，分配时钟已经成为一个越来越困难的任务。最近发布的芯片运行在超过2GHz的时钟频率。未来ULSI芯片的性能预测将在未来5-10年内达到20 GHz。这意味着整个芯片的总时钟偏移需要保持在5 ps以下，以便将时钟偏移量控制在总时钟周期的10%以内。这个问题将进一步加剧的急剧增加，在未来的处理技术超过50纳米代的过程中的变化。此外，当芯片包含越来越多的组件（门）时，芯片上的开关活动的差异将变化更大，从而导致温度和电源噪声的更大的芯片上变化，这些变化是时变的。这里提出的研究是为了探索一个显着不同的设计范式，为未来的时钟网络将动态地适应芯片的操作环境，以执行实时的抗扭斜功能的时钟信号的设计和分配。主动去偏斜使用片上有源器件（如延迟锁定环（DLL））来检测和减少芯片上任意两点之间的偏斜。所提出的研究地址的问题包括：给定芯片架构和特性（开关，泄漏和密度）的芯片上使用的块，什么是最佳的拓扑结构的自调整去扭斜网络，必须是稳定的？考虑到芯片的性能要求，芯片可以容忍的去偏斜网络的最大延迟是多少？抗扭斜电路的分辨率是多少？这对时钟网络的整体性能有何影响？研究包括理论上的广泛探索，以确定这种去偏斜方法的实用性。整个去偏斜系统的数学模型被制定为一个多输入，多输出（MIMO）离散时间动态系统。目前正在根据该模型进行稳定性分析。这种方法使用的结果，从鲁棒控制理论，可以保证稳定性，即使扰动系统。

During the last several decades, the clock rate and the level of integration of VLSI chips have reached a level that distributing clocks has become an increasingly difficult task. The most recently released chips run at more than 2GHz-clock rate. The performance projection for future ULSI chips will be up to 20GHz in the next 5-10 years. This implies that the overall clock skew needs to be kept under 5ps across the chip in order to control the amount of clock skew to be within 10% of the total clock cycle. This problem will be further exacerbated by the steep increase in process variations in future processing technologies beyond 50nm generations. Furthermore, when chips contain more and more components (gates), the disparity of switching activities on chip will vary more widely resulting in greater on-chip variations of temperature and supply noise, which are time-variant. The research proposed here is intended to explore a dramatically different design paradigm for designing and distributing clock signals for the future where the clocking networks will be dynamically adapted to chip's operating environment to perform a deskewing function in real-time. Active deskewing uses on-chip active devices such as delay-locked loops (DLLs) to detect and reduce skews between any two points on the chip. The issues the proposed research addresses include: Given a chip architecture and the characteristics (switching, leakage, and density) of the blocks used on the chip, what is the optimal topology of the self-adjusting deskewing network that must be stable?Given the performance requirements for the chip, what is the maximum latency of the deskewing network the chip can tolerate?What is the resolution of deskewing circuits? And how does this affect the overall performance of the clock network?Research includes an extensive exploration theoretically to determine the practicality of such a deskewing approach. A mathematical model for the entire deskewing system is formulated as a multi-input, multi-output (MIMO) discrete-time dynamic system. A stability analysis based upon the model is being developed. This approach uses results from robust control theory that can guarantee stability even for perturbed systems.