ITR: A Completely Integrated Processor-Memory-Interconnect Architecture for Data Intensive Applications

提出了一种新的、完全集成的处理器-存储器-互连(CI-PMI)体系结构模型，适用于一系列数据密集型应用。与现有的内存中处理器(PIM)结构相比，CI-PMI方法更完整地集成了处理、存储和互连。这是从大容量存储器的经典体系结构开始的，即以存储模块为叶子的解码器的二叉树，以H树的形式布局。在所提出的模型中，在存储器解码器树的不同级别添加一种或多种特定于应用的计算元件的副本，将期望的功能添加到存储器解码器以增强它们作为互连的作用以及支持期望的计算，并且如果需要，在特定于应用的处理器、存储模块和解码器之间添加额外的互连。建议的架构将为数据密集型应用程序开发和演示，即用于MPEG编码的运动估计。建议的研究结果将用于增加一个高级课程，该课程将在南加州大学和加州大学学院教授。本课程将自上而下地介绍先进的内存中处理器架构，包括本项目开发的架构。建议的研究将推进计算机架构、VLSI和VLSI CAD的最新发展，为日常计算和信息检索、交换和管理带来更快、更便宜的设计。

A new, completely-integrated processor-memory-interconnect (CI-PMI)architecture model suitable for a range of data-intensiveapplications is proposed. Compared to the existing processor-in-memory(PIM) architectures, the proposed CI-PMI approach integrates morecompletely the processing, memory, and interconnect. This is achievedby starting with the classical architecture of high capacity memory,namely, a binary tree of decoders with memory modules as leaves, laidout as an H-tree. In the proposed model, copies of one or more typesof application-specific computing elements are added at differentlevels of the memory decoder tree, desired functionality added to thememory decoders to augment their role as interconnects as well as tosupport desired computation, and, if necessary, additional interconnectsadded between the application-specific processors, the memory modules,and the decoders. The proposed architecture will be developed anddemonstrated for a data-intensive application, namely motion estimationfor MPEG encoding.The results of the proposed research will be used to augment oneadvanced class, to be taught at USC as well as UCI. The class willtake a top-down view of advanced processor-in-memory architecturesincluding those developed in this project.The proposed research will advance the state of the art in computerarchitecture, VLSI, and VLSI CAD, leading to faster and cheaper designsfor day to day computation and information retrieval, exchange, andmanagement.