ITR-(ASE+NHS)-(int): A Digital System Paradigm For Yield Enhancement and Graceful Degradation Via Error Acceptance

ITR-（ASE+NHS）-（int）：一种通过误差接受提高成品率和优雅降级的数字系统范例尽管对改进制造工艺进行了广泛的研究，但工艺参数的高度变化、更高的缺陷密度和对外部噪声的更高敏感性将抑制VLSI的持续缩放。我们提出了两个概念，即容错和可接受的操作，以方便不精确的计算：这些概念系统地捕捉的事实，越来越大的一类数字系统可以是有用的，即使他们不完全符合严格的设计规范。我们建议开发一个系统的方法，这类数字系统的设计和测试，将利用容错的概念，使规模，速度和成本的显着改善。在拟议的方法中，系统规范将包括对系统输出错误类型的描述，以及可容忍的严重程度阈值。设计方法将利用这些信息，以获得设计，提供更高的性能和/或更低的costs. In未来15年，所提出的方法将提供显着的改进规模，速度和成本的广泛的一类数字系统，包括许多组成NHS。这将有助于开发和更广泛地部署在语音处理、自然语言口语实时翻译和生物识别等领域具有先进功能的设备。

AbstractITR-(ASE+NHS)-(int): A Digital System Paradigm For Yield Enhancement and Graceful Degradation Via Error AcceptanceDespite extensive research into improving fabrication processes, continued VLSI scaling will be inhibited by high variations in process parameters, higher defect densities, and higher susceptibility to external noise. We propose two notions, namely error-tolerance and acceptable operation, to facilitate imprecise computation: these notions systematically capture the fact that an increasingly large class of digital systems can be useful even if they do not perfectly conform to a rigid design specification. We propose to develop a systematic methodology for design and test of this class of digital systems that will exploit the notion of error tolerance, to enable dramatic improvements in scale, speed, and cost. In the proposed methodology, system specification will include a description of the types of errors at system outputs, and the thresholds on their severities, that are tolerable. The design methodology will exploit this information to obtain designs that provide higher performance and/or lower costs.Over the next 15 years, the proposed approach will provide dramatic improvements in scale, speed, and cost for a wide class of digital systems, including many integral to NHS. This will enable development and wider deployment of devices with advanced capabilities in areas such as speech processing, real-time translation of spoken natural languages, and biometrics.