Exploring Design Approaches and Fault Tolerance in Nano Streaming Processors

近年来，纳米技术已经成为新的计算结构的一个有前途的技术平台。基于纳米管和纳米线的硬件已经进行了大量的研究：这些结构的特征尺寸只有几纳米。该项目的主要目标是开发纳米级计算结构，电路和架构的基础，这将利用纳米级器件的独特属性。特别是，纳米器件的缺陷密度预计将远远大于传统的微电子器件。将开发允许包含故障的电路继续运行的容错技术。容错总是需要引入冗余;容错设计涉及在这种冗余所施加的开销和可靠性的可用增益之间进行权衡。将开发基于纳米技术的综合计算机体系结构的设计工具。这些工具将考虑到现实的参数和物理约束，影响纳米电路的位置，并允许设计师研究纳米技术的架构权衡。

Nanotechnology has emerged in recent years as a promising technological platform for new computational structures. Substantial research has been carried out into hardware based on nanotubes and nanowires: structures which have feature sizes of just a few nanometers. The principal objective of the project is to develop the foundations for nanoscale computational structures, circuits and architectures, that will take advantage of the unique properties of nanoscale devices. In particular, the defect density of nanodevices is expected to be much greater than that of conventional microelectronic devices. Fault-tolerance techniques to allow circuits containing faults to still continue to function will be developed. Fault tolerance always requires introducing redundancy; fault-tolerant design involves making tradeoffs between the overhead imposed by such redundancy and the available gain in reliability. Design tools for synthesizing computer architectures based on nanotechnology will be developed. Such tools will take into consideration realistic parameters and physical constraints that affect the placement of nanocircuits, and will allow the designer to study architectural tradeoffs in nanotechnology.