Statistical Tools and Methodologies for Timing Validation and Silicon Debug

随着纳米制造技术的进步，由于参数变化的增加，芯片设计和芯片制造之间的差距变得越来越大。这一差距导致先进生产线的好零件出合格率下降，造成制造资源的重大损失。弥合差距需要在设计验证和硅调试方面使用新颖的工具和方法。本课题提出了一种新的验证和调试框架，促进了制造测试和设计仿真之间的自动信息流。结合计划的教学活动，本研究提出了一个连贯的软件框架，由三个部分组成：(1)基于模式的统计时序分析，(2)硅仿真，(3)测试数据挖掘。基于模式的统计时序分析的主要目标是实现健壮的测试开发和硅片调试。它是一种仿真工具，用于分析测试结果对模型假设和过程变化的敏感性。为了更好地理解设计和制造之间的差距，需要仔细研究不同参数变化如何相互作用以影响芯片性能。为了实现这项研究，PI建议开发一个硅模拟器，该模拟器暴露了仿真环境中性能变化的复杂性。在第三部分，将开发新的数据挖掘和统计学习技术，从测试数据中提取有用的设计信息。结合测试模拟工具和测试数据挖掘技术的新型调试和验证方法将被开发出来，以促进设计和制造之间的融合。这项研究补充了设计自动化和测试领域的其他研究工作。统计静态时序分析的研究旨在提供新的工具，以更好地应对达到时序闭合的变化，而所提出的框架旨在解决时序闭合后的问题。延迟测试的研究旨在提高频率相关制造缺陷的筛选效率，而所提出的框架旨在有效诊断设计行为与硅片行为之间的差异。本研究介绍了数据挖掘和统计学习技术的新应用。虽然大多数数据挖掘技术侧重于模型的可预测性和准确性，但所提出的技术将侧重于模型的可解释性和诊断性。这些新技术可以激发数据挖掘社区开发用于设计自动化和制造测试应用的新方法。通过该项目开发的技术将被转移到领先的半导体企业。这些技术将改进其设计和测试方法，并继续推动制造技术走向前沿。

ABSTRACT0541192Wang, Li-ChungU of Cal Santa BarbaraProject Title: Statistical Tools and Methodologies for Timing Validation and Silicon DebugWith the advances to nanometer manufacturing technologies, the gap between chip design and chip manufacturing has become wider due to increased parametric variations. This gap causes the reduction in percentage of good parts coming out of an advanced manufacturing line, resulting in significant loss of manufacturing resources. Bridging the gap demands novel tools and methodologies in design validation and silicon debug. This project proposes a novel validation and debug framework that facilitates the automatic information flow between manufacturing testing and design simulation. Integrated with the planned educational activities, the research proposes a coherent software framework consists of three components: (1) pattern-based statistical timing analysis, (2) silicon emulation, (3) test data mining. The primary goal of pattern-based statistical timing analysis is to enable robust test development and silicon chip debug. It is a simulation tool that analyzes the sensitivity of test results with respect to model assumptions and process variations. To better understand the gap between design and manufacturing, a careful study on how different parametric variations interact to impact chip performance is required. To enable this study, the PI proposes the development of a silicon emulator that exposes the complexity of performance variations in a simulation environment. In the third component, novel data mining and statistical learning techniques will be developed to extract useful design information from test data. Novel debug and validation methodologies that incorporate the test simulation tool and test data mining techniques will be developed to facilitate the convergence between design and manufacturing. This research complements other research efforts in the design automation and test areas. While the research in statistical static timing analysis aims to provide new tools to better cope with variations in reaching timing closure, the proposed framework aims to resolve the issues after the timing closure. While the research in delay testing aims to enhance the effectiveness of screening frequency-dependent manufacturing defects, the proposed framework aims to effectively diagnose the discrepancies between design behavior and silicon chip behavior. This research introduces novel applications of data mining and statistical learning techniques. While most data mining techniques focus on model predictability and accuracy, the proposed techniques will focus on model interpretability and diagnosis. These new techniques can inspire the data mining community to develop novel approaches to be applied in design automation and manufacturing test applications. Technologies developed through the project will be transferred to the leading semiconductor companies. These technologies will improve their design and test methodologies and continue the push of manufacturing technologies to the cutting edge.