CPA: Reconfigurable On-chip Network Design Framework for Fault-Tolerance and Performance

面向容错和性能的可重构片上网络设计框架传统的容错互连网络设计通常假设整个链路和/或路由器都有故障的粗粒度故障模型。粗粒度故障模型的解决方案主要集中在基于拓扑的路由路径冗余或设计健壮的网络协议来检测和避免故障。这种粗粒度故障模型适用于计算机/主机和通信链路不可靠的多计算机网络、局域网和WAN。然而，粗粒度模型是不适合的片上网络，其中常见的故障是（a）瞬态故障，（B）瞬时永久故障和（c）永久故障发生在整个集成芯片的寿命。该项目有两个目标。首先，它旨在量化片上网络的各种组件的敏感性（即，缓冲器、路由逻辑、仲裁器、交换机和链路）在它们的架构脆弱性因子（AVF）、成品率调整的吞吐量和平均故障时间（MTTF）方面与三类故障相关联。第二个目标是设计保护和可重构的网络，以尽量减少其脆弱性的故障，并提供优雅的性能下降时，故障导航的机制。

Reconfigurable On-chip Network Design Framework for Fault-Tolerance and Performance Traditional fault-tolerant interconnection network design typically assumes a coarse-grain fault model where entire links and/or routers are faulty. Solutions to the coarse-grain fault model broadly focus on topology-based routing-path redundancy or designing robust network protocols to detect and avoid faults. This coarse-grain fault model is appropriate for multicomputer networks, LANs and WANs where computers/hosts and the communication links are unreliable. However, the coarse-grain model is unsuitable for on-chip networks in which the common faults are (a) transient faults, (b) manufacture-time permanent faults and (c) permanent faults that occur over the lifetime of the integrated chip. This project has two aims. First, it aims to quantify the susceptibility of the various components of on-chip networks (i.e., buffers, routing logic, arbiters, switches and links) to the three classes of faults in terms of their architectural vulnerability factors (AVFs), yield-adjusted throughput and mean time to failure (MTTF). The second goal is to design protected and reconfigurable networks to minimize their vulnerability to faults and to provide mechanisms for graceful performance degradation when faults are navoidable.