Continuous Technology Management

该项目研究了持续技术管理（CTM），即功耗、片上噪声、粒子撞击漏洞、工艺变化和老化缺陷的持续运行时间管理。 在CTM中，每个处理器内核都被划分为具有集成监控和测试支持的区域，并且能够将参数（例如电源电压）推到最差情况推荐限制以下。 保护带在运行时通过局部压力测试和具有相同功能的相邻单元上的冗余安全操作的组合来动态确定。 这些保护带应该几乎总是低于在设计时可以静态实现的，因此可以产生额外的性能或功率节省。 保护带的频繁周期性重新评估允许系统耐受环境中的大的、缓慢的变化（例如，随着海拔的升高中子通量增加），而不必求助于恒定冗余及其相应的性能和功率成本。 这种支持在多个层中实现，包括硬件微架构、监视器、诊断和控制（本地和全局控制器以及系统级中间件）。 该项目的成功完成将对美国半导体行业产生广泛影响。 上述挑战是生产从手持设备到超级计算机的高性能、功率高效、鲁棒的计算平台的能力的严重障碍。

This project investigates Continuous Technology Management (CTM), the continuous runtime management of power dissipation, on-chip noise, particle strike vulnerability, process variations, and aging defects. In CTM, each processor core is divided into regions with integrated monitoring and test support, as well as the ability to push parameters (such as supply voltage) below worst case recommended limits. Guard bands are determined dynamically at runtime through a combination of localized stress testing and redundant safe operation on an adjacent unit with the same functionality. These guard bands should be almost always lower than can be achieved statically at design time and therefore can yield additional performance or power savings. Frequent periodic reassessment of guard bands permits the system to tolerate large, slow changes in environment (such as an increase in neutron flux with higher elevation) without having to resort to constant redundancy and its corresponding performance and power costs. This support is implemented in multiple layers comprising the hardware microarchitecture, monitor, diagnostic, and control (local and global controllers and system level middleware). The successful completion of this project will have broad implications for the U.S. semiconductor industry. The aforementioned challenges are serious obstacles to the ability to produce high performance, power efficient, robust computing platforms across the spectrum from handhelds to supercomputers.