CRI: Comprehensive, Pre-RTL Architectural Thermal Modeling

弗吉尼亚大学的主要研究人员将为VLSI设计的早期设计阶段热建模开发一个社区资源工具集。热极限被工业界广泛认为是对未来VLSI设计能力的严重限制。减小规模、增加晶体管和功能的努力增加了热负载，同时增加了功率泄漏、故障和电气使用。该项目将开发用于预RTL设计阶段的工具，在该阶段有最大的机会来解决计算，封装和冷却选择以及与其他组件交互的空间和时间特性。用户将能够模拟完整的系统;工具将得到验证，允许彼此之间以及系统模拟器之间的灵活连接;它们将支持快速学习。这些工具将使广泛的研究和教育社区能够参与电力感知架构研究。这些工具将建立在弗吉尼亚州现有的芯片建模能力的基础上。更广泛的影响包括为广大社区或研究人员和教育工作者提供新的研究和教育基础设施，支持能够解决工业中这些紧迫问题的工程师的教育和培训，以及为妇女，少数民族和高中生提供的外展计划。

The principal investigators at the University of Virginia will develop a community resource toolset for early design stage thermal modeling of VLSI designs. Thermal limits are widely cited by industry as a severe limit on future VLSI design capabilities. Efforts to reduce scale, increase transistors and functionality increase thermal loads while increasing power leakage, faults, and electrical usage. This project will develop tools for the pre-RTL design stage where there is the greatest opportunity to address space and time characteristics of computation, packaging and cooling choices and interactions with other components. Users will be able to model full systems; tools will be validated, allow for flexible connections with each other as well as system simulators; and they will support rapid learning. The tools will enable a broad research and education community to participate in power-aware architecture studies. The tools will build on Virginia's existing chip modeling capabilities. Broader impacts include providing new research and education infrastructure to a wide community or researchers and educators, supporting the education and training of engineers who can solve these pressing problems in industry, and an outreach program for women, minorities, and high school students.