Heterogeneous Multi-core Architectures from Homogeneous Arrays using Configurable Interconnect

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Recent trends in microprocessor design are shifting toward incorporation of heterogeneous core types onto the same die. However, current design techniques provision only a fixed set of cores and suffer from poor resource utilization when the workload is not a good match for those resources and the system cannot efficiently employ all resources simultaneously. Hardware should adapt the organization of the heterogeneous cores in response to dynamic behavior. This project lays the groundwork for realizing such a dynamic heterogeneous processor - the field programmable core array (FPCA) - that is capable of simultaneously implementing many heterogeneous architectural configurations on a configurable, homogeneous platform. The required flexibility will be provided through a combination of architecture, circuit, and EDA advances. The intellectual merit of this project is the technique of separating a processor's front end and functional units into homogeneous pools of building blocks, and development of a programmable interconnect allowing these building blocks to be coupled and decoupled dynamically, enabling efficient intra- and inter-core connectivity and the assembly of a variety of heterogeneous organizations. The broader impact will be the development of a new design paradigm that allows the same chip to be used for a wider range of markets and workloads. This reduces design and procurement costs, while improving programmer productivity - all of which will provide economic and social benefits. This project also includes education and outreach activities, including improved teaching of emerging programming models and outreach to high school students and underrepresented groups.