Communication and Synchronization Mechanisms for Emerging Multi-Core Processors

CCF-CPA：新兴多核处理器的通信和同步机制Sandhya Dwarkadas和Michael L.Scott 2007年3月由于芯片密度和功率限制的增加，显式硬件并行将很快主导计算频谱，多核芯片将取代整个台式机和笔记本电脑市场的单处理器。如果要有效地使用这些芯片，新的编程模型必须简化编写多线程代码的任务。这些模型反过来又必须得到体系结构机制的支持，以最大限度地减少数据通信和同步的成本。受赞助的研究使用硬件和软件相结合的方法来解决主流并行性的挑战。关键思想是确定跨各种应用程序和编程模型的常见时间关键型操作，这些操作可能会被新的体系结构机制加速或简化，然后以尽可能通用的方式设计这些机制。通过尽可能地将策略留给软件，该策略旨在最大限度地利用自适应和特定于应用程序的协议来提高可伸缩性。候选硬件机制包括：更新时警告，它利用高速缓存一致性进行快速的基于事件的通信；可编程数据隔离，它允许处理器隐藏本地写操作以进行推测和事务处理；以及自适应协作高速缓存，它重新设计芯片上一致性协议，以适应不同的数据共享模式，并在核之间高效地传送值。将主要在硬件一级研究这些机制，但也将开发系统软件，以支持新的编程模型(事务、推测)，并能够对性能和可编程性进行详细评估。通过更好的并行编程模型和有效的实施，受资助的研究旨在未来十年继续进行计算革命。通过有效使用更多更简单的内核，它还满足了降低主流处理器能耗的迫切需求。驾驶应用程序将来自多个来源，包括与生物学、天体物理学和化学方面的大学同事、人工智能和互联网服务部门的同事以及数据挖掘方面的本地和远程同事的合作努力。编程模型和任务将包括事务计算、推测性执行以及性能和正确性调试。

CCF-CPA: Communication and Synchronization Mechanisms for Emerging Multi-Core ProcessorsSandhya Dwarkadas and Michael L. ScottMarch 2007As a result of increasing chip density and power limitations, explicit hardware parallelism will soon dominate the computing spectrum, with multicore chips replacing uniprocessors throughout the desktop andlaptop markets. If these chips are to be used effectively, new programming models must ease the task of writing multithreaded code. These models must in turn be supported by architectural mechanisms thatminimize the cost of data communication and synchronization.The sponsored research addresses the challenge of mainstream parallelism using a combined hardware-software approach. The key idea is to identify common time-critical operations, across a variety of applications and programming models, that might be accelerated or simplified by new architectural mechanisms, and then to design those mechanisms in as general a fashion as possible. By leaving policy tosoftware whenever possible, this strategy aims to maximize opportunities for adaptive and application-specific protocols that increase scalability. Candidate hardware mechanisms include alert-on-update, which leverages cache coherence for fast event-based communication; programmable data isolation, which allows a processor to hide local writes for speculation and transactions; and adaptive cooperative caching, which re-engineers the on-chip coherence protocol to accommodate different patterns of data sharing and to communicate values efficiently between cores. These mechanisms will be studied mainly at the hardware level, but system software will also be developed to support new programming models (transactions, speculation) and to enable detailed evaluation of performance and programmability.Through better parallel programming models and efficient implementations, the sponsored research aims to continue the computing revolution over the course of the coming decade. By enabling the effective use of larger numbers of simpler cores, it also addresses the critical need to reduce energy consumption in mainstream processors. Driving applications will be drawn from multiple sources, including collaborative efforts with University colleagues in Biology, Astrophysics, and Chemistry; department colleagues in Artificial Intelligence and Internet services; and local and remote colleagues in data mining. Programming models and tasks will include transactional computing, speculative execution, and performance and correctness debugging.