CPA: Collaborative Research: Formal Techniques for Designing Globally Asynchronous and Locally Synchronous Systems (FMGALS)

协作性提案ID(S)：0702316和0702539标题：：协作性研究：设计全球异步和本地同步系统的正式技术(FMGALS)PI：SanDeep K.Shukla(弗吉尼亚理工大学)和Kenneth Stevens(犹他州大学)全球异步和本地同步(GALS)设计的势头增强是由三个因素推动的。首先，由于cmos技术特征尺寸的减小和千兆赫兹范围内时钟频率的增加，时钟周期正在向在整个芯片中高效同步时钟变得越来越困难的极限递减。其次，如果所有IP不需要针对相同的时钟方案进行优化，那么基于IP重用的片上系统(SoC)设计变得更加容易；最后，增加时钟缓冲器、全局中继器和时钟树的功耗是一个日益增长的工业界关注的问题。然而，正确地设计GALS系统是容易出错和困难的。除了少数例外，外部学术界几乎不存在异步设计工具和方法。对GALS设计工具和方法的研究势在必行。鉴于这些问题的微妙和复杂，我们认为，将任何GALS方法置于正式方法中是重要和必要的。将协议真正实施到芯片结构中并通过实验验证此类设计的有效性对于设计方法的广泛接受是必要的。在该项目中，弗吉尼亚理工大学和州立大学以及犹他大学的团队将合作开发用于设计和试验各种GALS解决方案的正式基础，并实际在芯片上制造此类解决方案以校准解决方案。除了发明新的GALS技术以及正式捕获和验证协议的方法的研究和教育影响之外，该项目的更广泛的影响将构成协作团队工作和培训学生在分布式开发环境中工作。将本科生纳入研究，并特别努力将少数民族学生纳入项目。

Collaborative Proposal ID(s): 0702316 and 0702539Title:: Collaborative Research: Formal Techniques for Designing Globally Asynchronous and Locally Synchronous Systems (FMGALS)PIs: Sandeep K. Shukla (Virginia Tech) & Kenneth Stevens (University of Utah)The increased momentum towards Globally Asynchronous and Locally Synchronous(GALS) design has been necessitated by three factors. First, due to decreasing feature size of CMOS technology, and increasing clock frequency in the gigahertz range, the clock period is diminishing towards a limit where efficient synchronous clocking throughout the chip is getting difficult. Second, IP reuse based System on Chip (SoC) design becomes easier if all IPs do not have to be optimized for the same clocking scheme, and finally, increasing power consumption in clock buffers, global repeaters and clock tree is a growing industrial concern.However, correctly designing GALS systems is error prone and difficult.Asynchronous design tools and methodologies are almost nonexistent outside academia with a few exceptions. Research towards tools and methodologies for GALS design is imperative. Given the subtlety and complexity of these problems, we believe that grounding any GALS methodology in formal methods is important and necessary. Real implementation of protocols into on-chip fabrics and experimental validation of the efficacy of such designs is necessary for the wide acceptance of the design methodologies.In this project, the Virginia Polytechnic and State University and the University of Utah teams will collaborate to develop a formal basis for designing and experimenting with the trade-offs of various GALS solutions, and actually fabricate such solutions on-chip to calibrate the solutions.Other than the research and educational impact of inventing new GALS techniques, and methodologies for formally capturing the protocols and verifying them, the broader impact of this project will constitute collaborative team work and training of students to work in a distributed development environment, inclusion of undergraduate researchers into research, and special effort of including minority students into the project.