CSR-PSCE,SM: Trade-offs Between Static Power, Performance and Reliability in Future Chip Multiprocessors

由于晶体管的增长速度超过了芯片设计中的设计和验证工作，现在很大一部分片上晶体管被分配给存储结构，例如缓存。这些存储结构所消耗的静态功率加剧了当前芯片设计所面临的功耗和热问题。为了降低静态功率，使用了困倦技术，其中存储结构的非活动组件可以置于低功率状态。不幸的是，困倦的功率状态增加了晶体管对瞬态误差的敏感性。在这些问题的激励下，本研究探讨了芯片多处理器中静态功耗、性能和可靠性之间的权衡。本研究的基本贡献是开发了一种新颖的混合分析/仿真框架，使设计人员能够评估降低静态功率对处理器可靠性和性能的影响。利用这一框架，本研究探索了芯片多处理器中新的缓存管理和缓存协议，以及这些新方案对计算机系统可靠性和性能的影响。该框架还可以进行扩展，以分析每个核心中其他存储结构（如重新排序缓冲区、分支预测表以及各种指令和调度队列）的功耗、性能和可靠性权衡。

As the transistor growth outpaced the design and verification effort in chip design, a large fraction of on-chip transistors are now allocated to storage structures, such as caches. The static power consumed by these storage structures worsen the critical problems of power and thermal issues faced by current chip designs. To reduce the static power, drowsy techniques are used, where inactive components of a storage structure can be placed in a low power state. Unfortunately, drowsy power states increase the susceptibility of transistors to transient errors. Motivated by these problems, this research explores the tradeoffs between static power, performance and reliability in chip multiprocessors. The fundamental contribution of this research is to develop a novel hybrid analytical/simulation framework that allows designers to evaluate the impact of reducing static power on processor reliability and performance. Using this framework this research explores new cache management and cache protocols in chip-multiprocessors and the impact of these new schemes on reliability and performance of a computer system. The framework can also be extended to analyze the power, performance and reliability tradeoffs of other storage structures inside each core such as the reorder buffer, the branch prediction tables, and various instruction and scheduling queues.