Physical Modeling of Low-K Dielectric Breakdown and the Estimation of Full Chip Lifetime

该奖项是根据2009年美国复苏和再投资法案（公法111-5）资助的，“最先进的芯片使用低k材料形成互连线路之间的绝缘体。低k材料的使用减少了电容，从而减少了芯片中晶体管门之间的传播延迟。为了减少延迟，每一代技术都涉及k值逐渐降低的低k材料。这些材料是通过增加孔隙度而形成的，其可靠性特性逐渐降低。了解用低k材料制造的芯片的可靠性是很复杂的，因为可靠性是完整互连系统的一个功能，包括低k材料、帽层和屏障。因此，材料不能孤立地研究，材料之间的界面在击穿中起主要作用。本研究通过建立击穿模拟模型及其对经验数据的校准，对多孔低k介电体的击穿有了全面的了解。在多孔低k材料中，由于界面的作用以及大量的缺陷和材料不规则性，后端介电击穿是复杂的。这项工作研究了微观水平上多孔材料和界面（帽层和屏障）的介电击穿，并建立了材料和界面在应力作用下的传导模型。模型的经验校准涉及消除结构内部和结构之间线宽变化和测试结构尖端场增强影响的新方法。这些模型是用来构建一个工具来分析一个完整的芯片布局。S对后端介质击穿的脆弱性。最终的工具应该显著降低制造风险和设计成本。

"This award is funded under the American Recovery and Reinvestment Act of 2009 (Public Law 111-5)"State-of-the-art chips use low-k materials to form the insulator between interconnect lines. The use of low-k materials reduces capacitance, which in turn reduces the propagation delay between the transistor gates in a chip. To reduce delay, each technology generation involves low-k materials with progressively lower k values. These materials are formed by adding porosity and have progressively degraded reliability characteristics. Understanding the reliability of chips built with low-k materials is complicated, because reliability is a function of the complete interconnect system, including the low-k material, the cap layer, and the barrier. Hence, the materials cannot be studied in isolation, and the interfaces among the materials play a major role in breakdown. This research is developing a comprehensive understanding of breakdown of porous low-k dielectrics through the development of simulation models of breakdown and their calibration to empirical data. Backend dielectric breakdown is complicated because of the role of interfaces and the large number of defects and material irregularities in porous low-k materials. This work studies dielectric breakdown at the microscopic level, in porous materials and at interfaces (cap layer and barrier), and builds models of conduction through materials and at interfaces under stress. Empirical calibration of models involves new approaches to eliminate the impact of within and between structure linewidth variation and of field enhancement at test structure tips. The models are used to build a tool to analyze a full chip layout?s vulnerability to backend dielectric breakdown. The resulting tool should significantly reduce manufacturing risk and design respins.