RIA: Statistical Design of Analog and Mixed Signal Circuits

RIA：模拟和混合信号电路的统计设计

• 批准号: 9211407
• 负责人: Linda Milor
• 金额: $ 10万
• 依托单位: University of Maryland, College Park
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1992
• 资助国家: 美国
• 起止时间: 1992-09-01 至 1996-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9211407&HistoricalAwards=false
• 关键词: RIA; Statistical; Design; Analog; Mixed

With the advent of high speed circuits and mixed analog-digital designs, it is important to make sure designs are insensitive to manufacturing process variations. Designs must protect against two types of faults: catastrophic-short and open circuits, and parametric where circuits fail due to parameters deviating too far from their nominal values. This research is on statistical simulation of analog and mixed signal systems. Three research problems are being pursued. First, a SPICE-based macromodeling approach to reducing the simulation time of analog components is being used. An algorithm for finding the best parameters, given the performance needs is being sought. Second, both circuit level and macromodel level statistical process models for analog components are being explored. Algorithms for worst case analysis and for computing parametric yield, which are attuned to the complex parameter models of the analog circuit manufacturing process are being developed. Third, a new catastrophic fault model is the basis of algorithms for efficiently computing catastrophic fault coverage of test sets. From this information catastrophic yield of analog components can be computed.

随着高速电路和模数混合电路的出现， 设计，重要的是要确保设计不敏感 制造工艺变化。 设计必须防止两个 故障类型：灾难性短路和开路，以及 由于参数偏离太远而导致电路失效的参数 从他们的名义价值。 这项研究是在统计 模拟和混合信号系统的仿真。 三个研究 问题正在处理中。 首先，基于SPICE的宏建模 减少模拟元件仿真时间的方法是 市.我们 给出了求最佳参数的算法， 正在寻求性能需求。 二是电路级 宏模型级统计过程模型 正在探索组成部分。 最坏情况分析算法 和计算参数产量，这是调谐到 模拟电路制造的复杂参数模型 进程正在制定中。 第三，一种新的突变故障模型 是有效计算灾难性事件的算法的基础 测试集的故障覆盖率。 从这个灾难性的信息 可以计算模拟元件的成品率。