SHF: Small: An Adaptive Architecture Fabric for Constructing Resilient Multicore Systems

随着半导体技术规模的不断缩小，构建容错、无缺陷的微处理器变得越来越困难。 更严格的设计约束、更低的工作电压和更高的功率密度导致电路更容易受到制造缺陷、瞬时故障和磨损相关故障的影响。预计未来的设计将由1000亿个晶体管组成，其中许多将由于制造缺陷而无法使用，并且许多将由于磨损和其他错误而随着时间的推移而失效。 传统的大型机和关键任务系统依靠冗余来克服此类故障。 可靠性基本上被视为一种税，以额外的硅面积的形式征收，用于对最终用户必须支付的结果进行不断的双重和三重检查，以确保正确的操作。 由于可靠性问题侵入台式机和手机环境，大规模冗余由于高成本和能源开销而不切实际。 本研究提出了StageNet，一种新型的微处理器架构，其中可靠性不是税收，而是内置于系统的自然运行。 StageNet是内省的，以实现对可靠性风险的持续监控和适应，并在细粒度级别上可重新配置，以最大限度地减少单个故障对系统的寿命性能影响。 StageNet由三个主要组件组成：一个自适应计算基板，使单个微处理器的动态重组，装甲缓存设计，以提供高缺陷容限与低面积开销的片上缓存，和一个动态适应系统，以管理应用程序的执行和组织的硬件在其生命周期。 这项研究的更广泛的影响是，它创造了处理故障晶体管的经济有效的方法，这将使嵌入式计算机扩散到生活的更多方面，其中鲁棒性和可靠性是当前的障碍。

As semiconductor technologies scale continues to shrink, building fault-tolerant, defect-free microprocessors becomes increasingly difficult. Tighter design constraints, lower operating voltages, and increasing power densities have lead to circuits that are more susceptible to manufacturing defects, transient faults, and wearout-related failures. It is anticipated that future designs will consist of 100 billion transistors, many of which will be unusable due to manufacturing defects and many will fail over time due to wearout and other errors. Traditional mainframes and mission-critical systems rely on redundancy to overcome such failures. Reliability is essentially viewed as a tax that is levied in the form of additional silicon area devoted to constant double and triple checking of results that end-users must pay to ensure correct operation. As reliability concerns invade the desktop and cellphone environments, large scale redundancy is impractical due to the high cost and energy overheads. This research proposes StageNet, a new style of microprocessor architecture in which reliability is not a tax, but rather built in to the natural operation of the system. StageNet is both introspective to enable continuous monitoring and adaptation to reliability hazards and reconfigurable at a fine-grain level to minimize the lifetime performance impact that individual failures have on the system. StageNet consists of three major components: an adaptive computing substrate that enables dynamic reorganization of individual microprocessors, armored cache designs to provide high defect tolerance with low area overhead for on-chip caches, and a dynamic adaptation system to manage the execution of applications and organization of the hardware over its lifetime. The broader impact of this research is that it creates cost-effective ways of dealing with faulty transistors that will enable the proliferation of embedded computers into more aspects of life, where robustness and reliability are current barriers.