SHF: Small: Collaborative Research: Fast Sign-Off of Nanoscale Memory: From Predictive Device Modeling to Statistical Circuit Synthesis

片上存储器的扩展受到了22 nm及以下节点过多工艺变化和可靠性下降的巨大挑战。在目前的实践中，为了在所有工艺、电压和温度条件下实现所需的性能，通常需要对测试硅进行完全定制的设计和广泛的实验。虽然这种昂贵的方法在当今的芯片设计中是可以接受的，但它极大地降低了设计生产率和可预测性。当不断增加的变化性质缩小了设计窗口并加剧了存储器设计的复杂性时，情况变得更加严峻。这项建议旨在开发创新的方法，通过无缝集成预测变异性模型、统计抽样方案、稳健的优化算法和高效的硅表征技术，实现在芯片路线图结束时及以后的芯片上存储器的快速签字。此外，这些新的成果将被整合到一个在线框架中，以对后硅存储器设计进行统计基准测试，帮助说明10纳米节点以外的存储器设计的各种机会。这项研究工作将促进对具有不可靠元件的可靠设计的基础研究，提高广泛应用的设计生产率，并加快新兴纳米电子器件的统计设计解决方案。此外，通过新颖的教育课程和基于网络的传播工具，该项目将把新开发的设计知识传授给不同的学生群体，他们将领导创造从计算、通信到消费电子等所有类型的未来纳米级综合系统。

The scaling of on-chip memory is tremendously challenged by the excessive amount of process variations and reliability degradation at the 22nm node and below. In current practice, full custom design and extensive experimentation on test silicon are often necessary to achieve the desired performance under all process, voltage, and temperature conditions. Although such an expensive approach is acceptable in today's chip design, it drastically reduces design productivity and predictability. The situation becomes even more severe when the ever-increasing nature of variations narrows the design window and exacerbates memory design complexity. This proposal aims to develop innovative methodologies that will enable fast sign-off of on-chip memory at the end of the silicon roadmap and beyond, through the seamless integration of predictive variability models, statistical sampling schemes, robust optimization algorithms, and efficient silicon characterization techniques. Furthermore, these new outcomes will be integrated into an online framework to statistically benchmark post-Si memory design, helping illustrate the diverse opportunities of memory design beyond the 10nm node. This research effort will facilitate fundamental research on reliable design with unreliable components, enhance design productivity for a wide range of applications, and expedite statistical design solution for emerging nanoelectronic devices. In addition, through novel education curricula and web-based dissemination tools, this project will transfer the newly developed design knowledge to a diverse population of students, who will lead the creation of future nanoscale integrated systems of all types, from computation, communication, to consumer electronics.