GOALI: Nanowire Broken-Gap Tunneling Field-Effect Transistors for High-Performance, Ultra-Low-Power Logic Applications

智力优势：拟议研究的目的是设计、制造和表征新型纳米线破裂间隙隧道场效应晶体管(NW BG-TFET)，这种器件具有通过同时实现低于60 mV/十的亚阈值斜率和可与MOSFET媲美的驱动电流来大幅降低计算系统功率的潜力。所提出的工作具有很强的智力价值，因为它解决了未来CMOS扩展的一个关键问题，即如何降低逻辑功耗。它通过探索一种新的器件概念来做到这一点，即尚未实验探索的NW BG-TFET。特别是，该项目旨在提供对器件设计和操作的所有方面的透彻了解，包括界面状态和陷阱辅助隧道效应的影响，如果这种新器件要像预期的那样发挥作用，必须充分了解这些机制。广泛的影响：拟议的项目可能对理解表面介导的传输在TFET和一般纳米级器件中的作用有实质性的好处。它还为研究生提供了一个理想的培训场所，因为产业协作使学生能够获得直接的行业互动，这将使他们更好地了解其研究工作的现实世界应用。该项目还为课堂教育提供了机会，因为该设备提供了一个影响并最终限制CMOS缩放的因素的理想范例。最后，K-12教育外展活动与这项工作紧密结合在一起，该项目提供了许多展示纳米技术的机会，这些纳米技术可以引起人们对工程和科学事业的总体兴奋。

Intellectual Merit: The purpose of the proposed research is to design, fabricate and characterize novel nanowire broken-gap tunneling field-effect transistors (NW BG-TFETs), devices that have the potential to substantially reduce power in computational systems by simultaneously achieving sub-60-mV/decade subthreshold slope and drive currents comparable to MOSFETs. The proposed work has strong intellectual merit as it addresses a critical problem for future CMOS scaling, which is how to reduce logic power consumption. It does so by exploring a new device concept, the NW BG-TFET that has not yet been experimentally explored. In particular, project intends to provide a thorough understanding of all aspects of the device design and operation, including the influence of interface states and trap-assisted tunneling, mechanisms that must be fully understood if this new device is to function as intended.Broader Impact: The proposed project could have substantial benefits for understanding the role of surface-mediated transport in TFETs and nanometer-scale devices in general. It also provides an ideal training ground for graduate students, in that the industrial collaboration allows students to obtain direct industry interactions that will better allow them to understand the real world applications of their research endeavors. The project also offers an opportunity for classroom education, as the device provides an ideal example of the factors that affect and ultimately limit CMOS scaling. Finally, K-12 educational outreach activities are tightly integrated into this work, and this project provides numerous opportunities for demonstrations of nanotechnology that can generate excitement about engineering and scientific careers in general.