SHF: Small: Methods for Diagnosis of Non-Classical Faults in Digital Circuits

本项目重点研究了代表现代超大规模集成电路器件故障行为的过渡延迟和桥接故障等非经典故障的诊断测试生成方法。虽然现有的VLSI电路测试工具包含了多年的研究，但它们只处理经典的卡滞故障。一个卡在故障是可检测的单一输入模式。转换故障的检测更为复杂，因为它需要两个模式的序列。此外，现有的工具可以找到检测故障但可能无法诊断故障的测试，即识别故障的确切原因。测试中使用的传统度量是故障覆盖率。本研究调查了使用一个新的指标称为诊断覆盖率测试的有效性，在他们的角色故障诊断。例如，为了区分两个故障，必须使用检测一个故障而不检测另一个故障的测试；这样的测试称为排他测试。本研究提供了新的算法来生成非经典故障的诊断测试，同时允许使用现有的测试工具。摩尔定律预测，超大规模集成电路芯片上的器件数量每18个月就会翻一番，这只是遵循了每个晶体管最低成本的趋势。使能技术的驱动因素是特征的缩小几何形状，允许更高的晶体管密度和速度。然而，纳米几何形状导致了更大的工艺变化。现代VLSI技术的测试有两个特点。首先，复杂的断层机制不再由经典的卡滞断层来表示。其次，增加的工艺变化对产量的影响要求测试以诊断为导向；必须识别故障，以便消除故障的原因。该项目的研究满足了先进VLSI技术的两种需求。

The research in this project focuses on diagnostic test generation methods for non-classical faults, such as transition delay and bridging faults, which represent the fault behaviors of modern VLSI devices. Although, the existing tools for VLSI circuit testing incorporate years of research they only deal with classical stuck-at faults. A stuck-at fault is detectable by a single input pattern. Detection of a transition fault is more complex because it requires a sequence of two patterns. Also, the existing tools find tests that detect faults and may not diagnose them, i.e., identify the exact cause of a failure. The traditional metric used in testing is fault coverage. This research investigates the use of a new metric termed diagnostic coverage for the effectiveness of tests in their role of fault diagnosis. For example, to distinguish between two faults one must use a test that detects one fault but not the other; such a test is called an exclusive test. This research provides new algorithms to generate tests for diagnosis of non-classical faults while allowing the use of the available testing tools.Moore's law prediction of the number of devices on a VLSI chip doubling every eighteen months simply follows the trend of minimum cost per transistor. The enabling technology driver is the shrinking geometry of features allowing higher transistor density and speed. Nanometer geometries have, however, led to greater process variations. Two characteristics separate the testing of modern VLSI technologies. First, the complex fault mechanisms are no longer represented by the classical stuck-at faults. Second, the impact of increased process variation on yield requires testing to be diagnostic-oriented; faults must be identified so that their causes can be eliminated. The research in this project addresses both needs of the advancing VLSI technology.