CSR: Small: Hardware Architectures for Data Mining at the Exascale

用于在大数据集中找到有用模式的算法和技术，统称为数据挖掘和信息可视化，对于研究人员在不同领域进行发现至关重要。数据挖掘的目标（以及一般的计算）在架构层面上引入了根本性的挑战，尽管GPU架构的发展部分是由这些挑战驱动的，但整体计算系统性能的增长速度并不与数据生成和收集的速度相同，从而扩大了挖掘算法的能力和真实世界数据挖掘系统的性能之间的差距。该项目研究了新的硬件/软件平台的设计，使现有的数据挖掘算法能够随着越来越大和复杂的数据集而扩展。在这样做的过程中，这个项目建立在当前的理解的数据挖掘应用程序的特点，不同于那些现代处理器目前设计的，类似于已经在信号处理和网络处理领域。该项目还研究了各种设计方法和计算模型，这些方法和模型可能会导致性能改进。最后，这个项目分析了算法精度和架构开销之间的内在权衡，试图概括精度和性能的权衡。预期的影响是，这些研究任务将有助于在硬件/软件接口的嵌入式系统设计的工作越来越多，并将有助于开发未来的混合多核计算平台的一部分。

The algorithms and techniques used to find useful patterns in large sets of data, collectively known as data mining and information visualization, have become vital to researchers making discoveries in diverse fields. The goals of data mining (and computing in general) at the Exascale have introduced fundamental challenges at the architectural level, and even though the evolution of GPU architecture has partly been driven by these challenges, overall computing system performance is not increasing at an equal rate as that of data generation and collection, thus widening the gap between the capabilities of mining algorithms and the performance of real-world data mining systems. This project investigates the design of new hardware/software platforms that will enable existing data mining algorithms to scale with increasingly large and complex datasets. In doing so, this project builds upon current understanding of the characteristics of data mining applications that differ from those for which modern processors are currently designed, similar to what already has been done in the signal processing and network processing domains. This project also studies a variety of design methodologies and models of computation that could lead to performance improvements. Finally, this project analyzes the inherent tradeoffs between algorithmic accuracy and architecture overhead in an attempt to generalize the accuracy and performance tradeoff. The expected impact is that these research tasks will contribute to the growing body of work in embedded system design at the hardware/software interface, and will help to develop a part of future hybrid multi-core computing platforms.