SHF: Small: Collaborative Research: VLSI Design Predictability Improvement By New Statistical Techniques in Timing Analysis, Delay ATPG, and Optimization

当今纳米级VLSI设计中最关键的挑战之一是分析和优化中缺乏可预测性。随着超大规模集成电路技术在纳米领域的不断扩展，超大规模集成电路系统不仅受到制造工艺的影响，而且还受到系统运行时环境的影响。日益显著的参数变化导致IC时序性能、功耗和其他产品指标的日益显著的变化。现有的VLSI统计分析技术不能准确有效地捕捉这些变化，这大大损害了设计优化和设计收敛，影响产品质量和上市时间。在这项工作中，PI计划开发基于信号概率的统计时序分析（SPSTA）技术，这将实现对不同输入的准确性能估计，而不是输入无关的悲观延迟界限。在这个项目中，PI建议建立在SPSTA的基础上，以实现一种新的，预测性和不那么悲观的VLSI实现方法。核心技术将跨越超大规模集成电路统计分析，延迟测试ATPG和优化技术，利用改进的可预测性。具体而言，该项目有三个重点领域，预计这些技术将优于现有的替代技术。该项目的结果对于半导体技术规模化的成本效益的持续至关重要（即，摩尔定律），并在未来几年保持半导体行业经济引擎的增长。拟议项目的更广泛的影响，可以进一步衡量一个强大的教育计划，包括课程开发和研究培训，将统计超大规模集成电路分析和优化技术纳入计算机工程计划在PI？机构，并进入课程基础设施，广泛和公开提供给其他人在线。根据他们十多年来的既定做法，研究所将通过出版物、行业合作和在线发布开源软件来广泛传播他们的研究成果。该项目还将使PI能够根据UT圣安东尼奥的少数民族学院地位扩大代表性不足群体的学生的参与;它将帮助旨在使圣安东尼奥区域经济转型为技术导向型经济的教育举措。

One of the most critical challenges in todays nanoscale VLSI design is the lack of predictability in analysis and optimization. As VLSI technology continues scaling in the nanometer domain, VLSI systems are subject to increasingly significant parametric variations coming from not only the manufacturing process but also the system runtime environment. Increasingly significant parametric variations lead to increasingly significant variations in IC timing performance, power consumption, and other product metrics. Existing VLSI statistical analysis techniques cannot accurately and efficiently capture such variations; this greatly compromises design optimization and design convergence, affecting product quality and time-to market. In this work the PIs plan to develop techniques for signal probability-based statistical timing analysis (SPSTA), which would achieve accurate performance estimates for different inputs, rather than input-oblivious pessimistic delay bounds. In this project, the PIs propose to build on the foundation of SPSTA to enable a new, predictive and less-pessimistic VLSI implementation methodology. Core techniques will span VLSI statistical analysis, delay test ATPG, and optimization techniques that exploit improved predictability. Specifically, there are three thrust areas in this project, and it is expected that that these techniques will outperform existing alternative techniques. The outcome of this project is critical to the cost-effective continuation of semiconductor technology scaling (i.e., Moore's Law), and to maintaining growth of the semiconductor industry's economic engine in the coming years. The broader impacts of the proposed project can be further measured by a strong education program including curriculum development and research training which incorporate statistical VLSI analysis and optimization techniques into the computer engineering programs at the PIs? institutions, and into course infrastructure that is broadly and openly available to others online. Following their established practices of well over a decade, the PIs will broadly disseminate their research results by publication, industry collaboration, and online posting of open-source software. This project will also allow the PIs to broaden participation of students from under-represented groups based on the minority institute status of UT San Antonio; it will help educational initiatives that are aimed at preparing the San Antonio regional economy to transform into a technology-oriented one.