SHF: Small: Measurement and Analysis of Regional Process Variations using Existing and Minimally Invasive On-Chip Embedded Resources

在先进技术节点中，精确控制集成电路(IC)制造过程的物理参数正变得越来越具有挑战性。这种控制的缺乏表现为功率变化和产品芯片延迟的增加。不幸的是，在最近的技术中，区域或芯片内的变化急剧增加，并且许多依赖于设计布局区域的上下文。跟踪工艺变化的传统方法，例如那些利用划线测试结构的方法，对于预测它们相邻的芯片内的功率和延迟变化已经变得越来越不有效。这推动了对嵌入式测试结构的需求，即那些直接结合到产品IC中的测试结构。这项研究旨在解决当前最先进的嵌入式测试结构设计中的不足，专注于真正嵌入的设计，并尽可能多地利用现有芯片基础设施。例如，将调查功率岛作为获得区域泄漏变化的方法，并将研究对扫描链架构的非侵入性修改作为测量区域延迟和功率变化的方法。建议工作的一个关键重点是改善嵌入式测试结构测量与实际芯片参数的相关性，例如，通过开发在实际操作条件下进行的测试和测量技术。研究生和本科生都将参与制造芯片的设计和测试，这将增强他们的教育经验，从而为IC行业拥有更多受过技术教育的劳动力做好准备。

Precisely controlling the physical parameters of an integrated circuit (IC) fabrication process is becoming more challenging in advanced technology nodes. This lack of control manifests as increasing levels of variations in power and delay in product chips. Unfortunately, regional or within-die variations have increased sharply in recent technologies, and many are dependent on the context of the design layout region. The traditional methods of tracking process variations, e.g., those that utilize scribe line test structures, have become increasingly less effective for predicting power and delay variations within chips that they are adjacent to. This has driven the need for embedded test structures, i.e., those incorporated directly into the product IC. This research is designed to address the deficiencies in the current state-of-the-art of embedded test structure design by focusing on designs that are truly embedded and leverage as much of the existing chip infrastructure as possible. For example, power islands will be investigated as a means of obtaining regional leakage variations and non-invasive modifications to the scan chain architecture will be investigated as a means of measuring regional delay and power variations.A key emphasis of the proposed work is to improve the correlation of embedded test structure measurements with actual chip parameters, e.g., by developing test and measurements techniques that are carried out under actual operating conditions. Both graduate and undergraduate students will participate in the design and test of fabricated chips, which will enhance their educational experience thus preparing them for a more technologically educated workforce for the IC industry.