NEB: Superlattice-FETs, Gamma-L-FETs, and Tunnel-FETs: Materials, Devices and Circuits for Fast Ultra-Lower-Power ICs

智力优势：该项目在2020年纳米电子学和超越竞赛下获得奖励，得到了美国国家科学基金会多个部门和部门以及半导体研究公司纳米电子学研究计划的支持。晶体管和集成电路（IC）缩放的进展已经放缓，部分原因是晶体管在小尺寸上运行的物理限制，但主要是因为随着复杂性和密度的进一步增加，功耗和功率密度变得过高。集成电路的功率密度是由晶体管和电路设计的相反约束决定的；电子热分布为低的关态耗散设定了最小的晶体管控制电压，而互连上的耗散能量随着电压的平方而增加。针对这些限制，提出了晶体管设计的根本改变。为了增加导通电流，提出了克服III-V半导体中所谓的态密度（DOS）瓶颈的设计，为传输中使用的那些增加额外的山谷，从而增加可以高速通过设备传输的电荷量。为了增加n沟道场效应晶体管（fet）的驱动电流和降低电压下集成电路的速度，III-V晶体管将首次在L（卫星）谷中传输，即L谷电子器件。它们将利用它们在快速载流子输运方向上色散的轻电子部分，并将利用重电子特性将多个能带打包到相同的？能量的空间。类似的态密度工程将应用于p沟道场效应管，利用应变和量子约束混合的轻空穴和重空穴态来实现。为了降低电源电压，陡峭的晶体管将被开发，其I-V特性变化比热分布快得多。除了已建立的仅具有中等导通电流的隧道注入器件外，还将开发大电流陡峭场效应管。它们在严格受限的能量范围的能带中使用输运，使用一维半导体超晶格产生。结合这两类晶体管，为低电压下的高驱动电流而设计的状态密度工程晶体管和为极低的非状态泄漏而设计的陡峭晶体管，该计划将探索提供低功耗和高速的新逻辑门设计。更广泛的影响：拟议的工作旨在提高速度和复杂性，并降低ic的功耗。该行业具有巨大的全球价值。参与者定期与VLSI行业互动，沟通正在进行的工作并寻求指导，并将在NSF计划中继续使用该模型。高速低功耗逻辑器件的发展将绕过目前限制VLSI速度和复杂性的功耗限制。该计划将使集成电路的速度和功耗限制的计算性能进一步大幅提高，有利于工业、商业和个人使用的应用。博士生将接受半导体材料、器件物理和集成电路设计方面的培训。他们的培训将强调系统和电路设计与设备设计的相互作用。仿真工具将由nanoHub开发并分发给全球用户社区。该项目将运营一个与NNIN附属的暑期实习项目，为8名本科生提供实验室研究环境的经验。

Intellectual merit: This project is awarded under the Nanoelectronics for 2020 and Beyond competition, with support by multiple Directorates and Divisions at the National Science Foundation as well as by the Nanoelectronics Research Initiative of the Semiconductor Research Corporation. Progress in transistor and integrated circuit (IC) scaling has slowed, in part because of physical limits of transistor operation at small dimensions, but primarily because power consumption and power density are becoming excessive as complexity and density are further increased. IC power density results from opposing constraints in transistor and circuit design; the electron thermal distribution sets a minimum transistor control voltage for low off-state dissipation, while the dissipated energy on interconnects increases as the square of voltage. Addressing these limitations, radical changes in transistor design are proposed. To increase the on-current, designs are proposed that will overcome the so-called density of states (DOS) bottleneck in III-V semiconductors, adding additional valleys to those used in transport, therefore increasing the amount of charge that can be transported through the device at a high velocity. To increase drive current in N-channel field effect transistors (FETs) and the IC speed at reduced voltages III-V transistors will be develop using for the first time transport in the L (satellite) valleys, i.e. L-valley electronics. These will use the light electron part of their dispersion in the transport direction for fast carriers and will use the heavy electron characteristics to pack multiple bands into the ?same? energy space. Similar density of states engineering will be applied to P-channel FETs, achieved using light- and heavy-hole states mixed by strain and quantum confinement. To reduce supply voltages, steep transistors will be developed, having I-V characteristics varying much more rapidly than a thermal distribution. In addition to established tunnel injection devices having only moderate on-current, high-current steep-FETs will be developed. These use transport in energy bands of tightly constrained energy range, produced using 1-D semiconductor superlattices. Combining these two classes transisto rs, state-density-engineered transistors designed for high drive currents at low voltage, and steep transistors designed for very low off-state leakage, the program will explore new logic gate designs providing low power and high speed.Broader Impacts: The proposed work seeks to increase the speed and complexity, and reduce the power consumption of ICs. The industry is of enormous worldwide value. The participants interact regularly with the VLSI industry, communicating ongoing work and seeking guidance, and will continue with this model in the NSF program. Development of high-speed yet low-power logic devices will circumvent present power-consumption limits now constraining VLSI speed and complexity. This program will enable further large increases in the speed and power-limited computational performance of ICs, benefiting applications in industry, commerce, and personal use. Ph.D. students will be trained in semiconductor materials, device physics, and IC design. Their training will emphasize the interaction of system and circuit design with device design. Simulation tools will be developed and distributed by nanoHub to a worldwide user community. The program will operate a summer internship program, affiliated with that of the NNIN, providing laboratory experience exposure to a research environment for 8 undergraduate students.