SHF: Small: Programming with Non-Coherent Memory

在多核系统的研究中，语言设计和程序分析工作的优势隐含地假设了底层连贯存储器的存在，以确保在处理器本地缓存上执行的更新的全局可见性。因为所有线程都有一致的数据视图，所以并发性bug纯粹是调度器驱动的线程交错和不充分的同步所带来的非确定性的结果。随着新的体系结构进步导致多核或多核平台支持数百个（可能是异构的）核心，自动执行内存一致性变得越来越复杂和昂贵。实际上，新的架构设计可能会牺牲局部一致性保证，以换取简单的基于商品的可伸缩设计，并配备有限程度的全局共享内存。针对这些平台的应用程序必须小心编写，不要对本地访问和修改的内存位置内容的一致性进行假设。在缺乏一致性的情况下，需要新的技术来恢复现在失去的抽象好处；这些问题在规模上变得更加严重。该提案的广泛影响与业界推动多核和多核处理器平台的努力有着明显的积极互动。这个项目将考虑新的方法，将在高级管理语言上下文中表达的一致性模型映射到非一致的体系结构平台上。在此过程中，它将考虑新的编程模型、抽象、分析和实现，以实现(a)尽可能避免一致性强制执行，(b)减少基于应用程序逻辑的一致性需求，(c)规范可用于通知实现专门的基于软件的一致性协议的复杂一致性需求，以及(d)将语言级内存模型与弱一致性架构集成。该项目将包含对不同抽象、分析和实现的正式、严格的开发，这些抽象、分析和实现能够自动构建新的协议族，这些协议族可以表达具有合理一致性语义的通信和计算动作的复杂聚合，即使在不一致的平台上执行也是如此。

The preponderance of language design and program analysis efforts in the study of multicore systems has implicitly assumed the presence of an underlying coherent memory that ensures global visibility of updates performed on processor-local caches. Because all threads witness a consistent view of data, concurrency bugs manifest purely as a consequence of unintended non-determinism introduced by scheduler-driven thread interleavings and inadequate synchronization. As new architectural advances lead to multicore or manycore platforms supporting hundreds of (potentially heterogenous) cores, automatically enforcing memory coherence becomes an increasingly complex and expensive proposition. Indeed, new architectural designs are likely to sacrifice local coherence guarantees in exchange for a simple commodity-based scalable design, equipped with a limited degree of global shared memory. Applications that target such platforms must be carefully written not to make assumptions about the consistency of the contents of memory locations accessed and modified locally. In the absence of coherence, new techniques are needed to recover the abstraction benefits that are now lost; these issues become exacerbated at scale. The broader impacts of the proposal have obvious positive interaction with industry efforts to promote multicore and manycore processor platforms.This project will consider novel ways to map consistency models expressed in the context of high-level managed languages onto non-coherent architectural platforms. In doing so, it will consider new programming models, abstractions, analyses, and implementations to enable (a) avoidance of coherency enforcement whenever possible, (b) reduction of coherency demands based on application logic, (c) specification of complex consistency requirements that can be used to inform the implementation of specialized software-based coherence protocols, and (d) integration of language-level memory models with weakly-coherent architectures. The project will subsume formal, rigorous development of different abstractions, analyses, and implementations that enable the automatic construction of new protocol families that express complex aggregates of communication and computation actions with sensible consistency semantics even when executed on non-coherent platforms.