Reduced Basis Element Methods for Thermal Modeling of Integrated Circuits

该项目的目标是开发集成电路（ic）热建模的“简化基元”技术。典型的数字集成电路是使用“技术库”中的标准单元来设计的，例如NOT， NAND， NOR和XOR门，触发器，加法器，乘法器和编码器/解码器等，每个单元都可以由多个通过金属互连连接的半导体晶体管组成。一个普通的集成电路将包含数百万个这样的标准单元，因此在计算上不可能对整个集成电路进行详细的热模拟。然而，由于计算系统的功率密度不断增加，开发准确有效的热模型变得越来越重要。此外，诸如绝缘体上硅（SOI）和3D堆叠等新技术只会加剧芯片加热问题。提出的工作将利用集成电路固有的几何重复来开发准确和计算效率高的热模型。将开发将集成电路单元和互连划分和分类为标准几何块的技术。然后将为这些模块创建紧凑的降阶模型，并将这些模型耦合在一起以预测整个集成电路的热行为。降阶模型将基于对单个单元的详细模拟数据进行适当的正交分解分析。因此，降阶模型将不需要任何特别的建模假设。耦合程序将采用借鉴不连续伽辽金有限元方法的方法。所提出的方法将使IC的热模拟具有与直接模拟相当的精度，其计算成本与当今的计算机器负担得起。当前的计算机比以往任何时候都能将更大的功率装入更小的封装中，这通常会导致严重的内部加热问题。计算机芯片设计人员必须根据集成电路中的温度分布做出妥协，并且需要高效准确的热模型来做到这一点。目前的模型是通过简化集成电路中热流的假设推导出来的，并没有提供详细的热数据。这些模型限制了设计师追求更先进的设计。这项工作旨在开发一种高效、高保真的工具，使更先进的设计能够被尝试，同时保持半导体行业的短设计周期。此外，将开发的基本框架将适用于任何具有重复几何特征的问题，如堆叠电池，太阳能电池板，热电模块等。因此，该技术可以在广泛的领域中实现基于第一性原理的高保真模拟。这些模拟将反过来使下一代先进设计成为可能。

The objective of this project is to develop "Reduced Basis Element" techniques for thermal modeling of integrated circuits (ICs). Typical digital IC's are designed using standard cells from "technology libraries", such as NOT, NAND, NOR and XOR gates, flip-flops, adders, multipliers and coders/decoders, etc., each of which may consist of a number of semi-conductor transistors connected by metal interconnects. A normal IC will contain millions of these standard cells and as such it is computationally infeasible to perform detailed thermal simulations of an entire IC. However, the development of accurate and efficient thermal models is becoming increasingly important because of the increasing power density of computing systems. Furthermore, new technologies such as silicon-on-insulator (SOI) and 3D stacking only exacerbate chip-heating problems. The proposed work will capitalize on the geometric repetition inherent in an IC to develop accurate and computationally efficient thermal models. Techniques for dividing and classifying an IC's cells and interconnects into standard geometry blocks will developed. Compact reduced order models for these blocks will then be created and these models will be coupled together to predict the thermal behavior of an entire integrated circuit. The reduced order models will be based on proper orthogonal decomposition analysis of detailed simulation data of individual cells. As such, the reduced order models will not need any ad-hoc modeling assumptions. Coupling procedures will use approaches borrowed from discontinuous Galerkin finite element methods. The proposed approach will enable thermal simulations of an IC with accuracy comparable to that of a direct simulation at a computational cost which is affordable with today's computing machinery. Current computers pack more power into smaller packages than ever before, which often results in significant internal heating problems. Computer chip designers must make compromises based on the temperature distribution in the integrated circuits and need efficient and accurate thermal models to do this. Current models are derived using simplifying assumptions about the heat flows in the integrated circuit and do not provide detailed thermal data. These models limit designers from pursuing more advanced designs. This work aims to develop an efficient, high-fidelity tool that will enable more advanced designs to be tried while maintaining the short design cycle of the semiconductor industry. In addition, the basic framework that will be developed will be applicable to any problem having repeated geometric features such as stacked-cell batteries, solar cell panels, thermoelectric modules, etc. Thus, this technique could enable first-principles-based high-fidelity simulations in a wide range of fields. These simulations will in turn enable the next generation of advanced designs.