CCF: SHF Small: Coping with the Slowing of Dennard's Scaling

Dennard的比例控制着集成芯片的功率、电压和频率的增长，在芯片上有源晶体管数量的指数增长方面，它与摩尔定律一样起到了重要作用。不幸的是，Dennard最近放慢了未来多核电源电压调整的速度，这可能会导致深色硅片，其中由于缺乏电力，越来越多的核必须保持断电。一种替代方案是通过为特定功能定制内核来提高能效。虽然暗硅选项明显降低了性能，但定制选项使多核走上了一条潜在的艰难道路，增加了硬件设计、验证和测试的工作量，并降低了可编程性。架构师面临的挑战是围绕Dennard扩展放缓的现实进行设计，同时避免两种严酷的后果(深色硅片或定制核心设计增加的成本/工作量)。该项目通过寻求一种替代的、温和(即，不费力)的多核扩展路径来解决上述挑战，同时保持在Dennard扩展放缓带来的功率范围内。该设计采用连续频率不定标，其中所有核心保持供电，并在每一代以连续较慢的时钟运行，以保持在功率预算内。一个分析模型(作为该项目的一部分而开发)，对有和没有连续频率取消定标的系统的性能做出了令人惊讶的预测，即尽管下一代(例如，亚GHz)的时钟相当慢，但连续的频率无定标将超过暗硅性能极限。本项目的主要研究目标是通过实际应用和详细的系统仿真来验证模型的预测。验证替代的、温和的多核扩展路径有可能为微处理器和计算机行业带来显著的好处。除了研究影响之外，该项目将教育组成部分整合到研究生和本科生课程中，有助于扩大其教育影响。

Dennard's scaling, which governs the growth of power, voltage and frequency of CMOS integrated chips, has been as instrumental as Moore's law in enabling the exponential growth of the number of active transistors on a chip. Unfortunately, the recent slowing down of Dennard's scaling of the supply voltage in future multicores may result in dark silicon where an increasing number of cores must be kept powered down due to lack of power. One alternative is to improve power efficiency by customizing the cores for specific functionalities. While the dark silicon option obviously degrades performance, the customization option puts multicores on a potentially arduous path of increased effort for hardware design, verification, and test, and degraded programmability. The challenge that architects face is to design around the reality of the slowing of Dennard's scaling while avoiding either of the two harsh consequences (dark silicon, or the increased cost/effort of customized core design).This project addresses the above challenge by pursuing an alternative, gentle (i.e., non-arduous) path for multicore scaling, while remaining within the power envelope imposed by the slowing of Dennard's scaling. The design employs successive frequency unscaling, where all the cores are kept powered and run at successively slower clocks every generation to stay within the power budget. An analytical model (developed as part of this project) for the performance of systems with and without successive frequency unscaling makes the surprising prediction that despite considerably slower clocks in later generations (e.g., sub-GHz), successive frequency unscaling would exceed the dark silicon performance limit. The key research goal of this project is to validate the predictions of the model with real applications and detailed system simulation. Validating an alternative, gentle path for multicore scaling has the potential to offer significant benefits for the microprocessor and computer industry. Beyond the research impacts, the project's integration of education components in both graduate and undergraduate curricula helps expand its educational impact.