SHF:Small: Benchmarking of Transient and Intermittent Errors and Their Application to Microarchitecture

在过去的几十年里，计算基础设施一直是我们社会经济进步的推动力。从药物发现到太空探索，每个科学和工程领域都依赖于计算机系统来准确分析复杂的数据集。从历史上看，计算精度在所有这些学科中都被认为是理所当然的，但这种观念正在改变。虽然晶体管尺寸的迅速缩小带来了指数级的功率和性能优势，但这种趋势也在计算机系统可靠性方面产生了一些不必要的副作用。有两种类型的错误将在不久的将来变得普遍：(1)多比特软错误，即α粒子和中子导致多个比特同时翻转，以及(2)间歇性错误，由于计算机寿命期间的应力积累而发生。因此，对这些错误对计算机芯片寿命的影响进行基准测试是至关重要的。只有准确地测量了影响，才有可能明智地部署解决方案以提高可靠性。由于任何保护方案都有成本，因此有必要了解正在考虑的特定保护方案（如奇偶校验或单错误纠正双错误检测代码）何时过多或过少。本课题提出了多比特软错误和间歇错误基准测试的两种解决方案。该项目将开发一种统一的方法，对任意保护方案（如交错、块级或字级纠错码）保护的缓存上的单比特和多比特软错误的影响进行基准测试。这样的基准测试框架将大大提高计算机设计人员客观评估各种保护方案的性能、功率和可靠性权衡的能力，以保护缓存。本研究还开发了一种方法来测试指令集架构（ISA）对间歇性错误的脆弱性。ISA规范中的每条指令都经过增强，以量化它对芯片底层微体系结构造成的压力。来自ISA的应力水平信息与芯片的操作条件相结合，连续监测应用程序执行期间的间歇性错误概率。芯片可靠性的任何不必要的下降，然后由软件异常处理程序来解决，这触发了易受攻击的代码的冗余执行。这些研究解决方案将产生更广泛的社会影响。基准测试对于客观地评估目前提出的各种解决方案的成本效益权衡是必不可少的，以解决可靠性问题。没有基准测试，构建满足可靠性规范的系统就像猜谜游戏。通过提供正确的工具集来启动及时的错误纠正和恢复机制，计算机设计人员可以显著降低提供可靠计算的成本。

Computing infrastructure has been a driving force for our socio-economic progress in the past several decades. From drug discovery to space exploration, every scientific and engineering domain relies on computer systems to accurately analyze complex datasets. Historically, computational accuracy has been taken for granted in all these disciplines, but this notion is changing. While rapidly shrinking transistor dimensions lead to exponential power and performance benefits, the trend is also creating several unwanted side effects in computer system reliability. There are two types of errors that will become prevalent in the near future: (1) multi-bit soft errors where alpha particles and neutrons cause multiple bits to flip at the same time, and (2) intermittent errors that occur due to stress accumulation over the lifetime of a computer. Thus it is critical to benchmark the impact of these errors on the lifetime of a computer chip. Only when the impact is accurately measured is it possible to judiciously deploy solutions to improve reliability. Since any protection scheme comes with a cost, it is necessary to understand when a particular protection scheme being considered, such as parity or single-error-correcting double-error-detecting code, is too much or too little. This project presents two solutions for benchmarking multi-bit soft errors and intermittent errors. This project will develop a unified methodology to benchmark the impacts of single-bit and multi-bit soft errors on caches protected with an arbitrary protection scheme, such as an inter-leaved, block-level or word-level error correcting code. Such a benchmarking framework will significantly enhance a computer designer's ability to objectively evaluate the performance, power, and reliability tradeoffs of various protection schemes proposed for protecting caches. This research also develops a methodology to benchmark the vulnerability of an instruction set architecture (ISA) to intermittent errors. Each instruction in an ISA specification is enhanced to quantify the amount of stress that it is expected to cause on the underlying microarchitecture of a chip. The stress level information from the ISA is combined with operating conditions of the chip to continuously monitor intermittent error probability during application execution. Any unwanted degradation in chip reliability is then tackled by software exception handlers, which trigger redundant execution of vulnerable code. Broader societal impact will result from these research solutions. Benchmarking is essential to objectively evaluate the cost-benefit tradeoffs of various solutions currently being proposed to tackle reliability concerns. Without benchmarking, building a system to meet reliability specifications is a guessing game. By providing the right set of tools to initiate just-in-time error correction and recovery mechanisms, a computer designer can significantly lower the cost of providing reliable computations.