I-Corps: An Ultra Low Power Multi-Constraint Physical Synthesis Tool for Chip Design

用于无数商业和消费电子产品的现代数字芯片非常复杂，目前消耗大量电力。根据国际能源署的数据，到2022年，信息和通信技术以及消费电子消耗的能源将增加一倍，到2030年将增加两倍，达到1700太瓦时。因此，必须设计基于新算法范例的有效的新CAD工具来设计数字芯片，以便它们消耗尽可能少的功率（而不降低性能）。这样做的好处包括降低电网消耗的电力（更环保的产品），降低冷却高性能服务器等高端系统的能源成本，延长便携式设备（如智能手机、笔记本电脑）和植入式医疗设备的电池寿命。在芯片设计流程（芯片设计经过的阶段序列）的关键物理合成（PS）阶段，将某些转换应用于电路，以便根据其他几个指标（例如，速度，产量，芯片面积/成本，温度）的约束对感兴趣的度量（例如，功率）进行优化。在传统的工业设计方法中，这些变换是依次应用的，并且每个变换在电路元件上依次应用，这导致次优设计（例如，更高的功耗）。该团队开发了一种名为DNF-PS的新型PS工具，可以同时准确地应用任何所需的变换集，并且在整个电路中同时进行，以优化功率，同时满足多种约束。因此，DNF-PS比目前的行业和学术工具有效得多。该项目的目标是通过以下方式探索和加强DNF-PS商业化的机会：1)了解和完善该计划的商业方面。2)通过更多的技术进步进一步加强DNF的性能和质量，其中一部分可以通过I-Corps项目的客户发现和互动方面来刺激。DNF-PS工具的商业领域是电子设计自动化（EDA）的成熟市场，拟议产品的潜在客户是众所周知的：芯片设计/半导体公司。这项活动的优点将包括以下部分：a)设计增强算法，以提高DNF-PS的接近最优特性（从而进一步降低功耗），从而使其对工业应用更具吸引力。b)在DNF-PS中开发分而治之策略，可以智能地将非常大的设计划分为更易于管理的块，并在不影响功耗优化的情况下分别优化每个块（从而提高运行时效率）。c)获取客户对DNF-PS的反馈，收集有关DNF-PS工具价值及其市场需求的市场情报。该提案的广泛影响将包括：a)使用DNF-PS可以高效地设计高功率优化芯片，并明显改善数千种电子产品的电池寿命和/或能源足迹。b)此外，由于基础DNF优化技术的显着功效，DNF- ps可以导致除功率外的其他指标（如速度，可靠性和芯片产量）芯片设计质量的显着跃升。这可以使这些指标至关重要的各种应用领域受益（例如，可靠性在汽车，飞机和航天电子中非常重要），并且还可以降低芯片成本（由于芯片产量增加）。

Modern digital chips that are used in a myriad of commercial and consumer electronic products, are very complex and currently consume significant amounts of power. According to the International Energy Agency, energy consumed by information and communications technologies as well as consumer electronics will double by 2022 and triple by 2030 to 1,700 terawatt hours. It is thus imperative to devise effective new CAD tools based on new algorithmic paradigms to design digital chips so that they consume as little power as possible (without degrading performance). The benefits of this will include lowering the power consumed off the power grid (environmentally friendlier products), smaller energy costs for cooling high end systems like high-performance servers, and longer battery lives for portable devices (e.g., smart phones, laptops) and implantable medical devices. In the crucial physical synthesis (PS) stage, of the chip design flow (the sequence of stages that the chip design goes through), certain transformations are applied to the circuit so that the metric of interest (e.g., power) is optimized subject to constraints on several other metrics (e.g., speed, yield, chip area/cost, temperature). In conventional industry design methodology, these transforms are applied sequentially, and each transform is applied sequentially across circuit components, which result in sub-optimal designs (e.g., higher power consumption). The team has developed a novel PS tool called DNF-PS which simultaneously applies any desired set of transforms accurately and also does so simultaneously across the entire circuit in order to optimize power, while satisfying multiple constraints. DNF-PS is thus much more effective than current industry and academic tools. The goal of this project is to explore and strengthen opportunities for commercializing DNF-PS via: 1) Learning about and refining the commercial aspects of the plan. 2) Further strengthening the performance and quality of DNF via a few more technological advances, part of which could be spurred by the customer discovery and interaction aspect of the I-Corps program. The commercial area of the DNF-PS tool is the well-established market of Electronic Design Automation (EDA), and the potential customers of the proposed product are well known: chip design / semiconductor companies. The merit of this activity will have the following components: a) Design of enhanced algorithms to improve the near-optimality properties of DNF-PS (thereby resulting in reducing power consumption even further), thus making it even more attractive for industry use. b) Developing divide-and-conquer strategies in DNF-PS that can intelligently partition very large designs into more manageable chunks, and optimize each separately (thus being more runtime efficient) without compromising power optimization. c) Getting customer feedback on DNF-PS and gathering market intelligence on the value of such a tool and its market requirements. The broader impact of this proposal will include: a) Highly power optimal chips can be designed efficiently with DNF-PS, with the obvious attendant improvements in the battery life and/or energy footprint of many thousands of electronic products. b) Furthermore, due to the significant efficacy of the underlying DNF optimization technology, DNF-PS can lead to a significant jump in chip design quality in other metrics besides power, like speed, reliability and chip yield. This can benefit various applications areas in which these metrics are paramount (e.g., reliability is very important in automotive, airplane and space electronics) and also reduce chip cost (due to increased chip yield).