SHF: Small: Enhancing Power, Performance, and Resource Efficiency of Many-core NoCs

考虑到计算系统在不断增长的环境中以各种形式无处不在地使用，计算的持续发展至关重要--从促进个性化医疗的可植入和可穿戴的生物医学设备，到促进高效交通和民用基础设施的嵌入式和智能传感器设备，到促进数据收集、挖掘、建模和发现的云服务器，再到涉及许多学科和部门的许多其他科学、经济和社会计算应用。半导体技术的不断进步和新的应用领域的不断出现，促使多核芯片多处理器(CMPS)得到了前所未有的发展，以满足日益增长的性能期望和未来系统日益严格的功率和资源限制。伴随着这种并行处理范例而来的是在单机或分布式系统中有效地互连数十到数百个芯片以及可能的数千个芯片的许多挑战。为了应对这些挑战，片上网络(或NoC)通信体系结构必须能够提供可扩展的性能，同时需要最少的资源和超低的功耗。本研究探讨了在多芯片处理器系统中提高片上网络功率、性能和资源效率的横切方法和技术。为了有效地利用电路级功率门控技术，探索了架构级支持。其目标是最大限度地节省静态功耗，最大限度地减少NoC的性能损失，同时在应用这些技术时节约整个系统的动态功耗和能量消耗。还探讨了最大限度地减少NOC资源和实现资源利用灵活性的创新方法。其目标是在平衡系统级权衡的同时提高NOC资源效率。该研究计划建立了一种系统的、全面的和基于经验的方法来研究多核化学机械抛光系统的有效通信架构，并有坚实的理论支持，这将导致设计出有前景的新方法和技术。除了对计算机领域的根本进步作出贡献外，这项研究还通过其扩大不同背景的人参与计算和劳动力发展的外联活动，对社会产生了更广泛的潜在影响。

Continued advancement of computing is of critical importance given the ubiquitous use of computing systems in various forms across a growing landscape-from implantable and wearable biomedical devices to facilitate personalized healthcare; to embedded and smart-sensor devices to facilitate efficient transportation and civil infrastructure; to cloud servers to facilitate data collection, mining, modeling and discovery; to many other scientific, economic, and social computing applications touching numerous disciplines and sectors. Unrelenting progress in semiconductor technologies and continual emergence of new application areas spur unprecedented development of many-core chip multiprocessors (CMPs) to satisfy increasing performance expectations and tightening power and resource constraints of future systems. Along with this parallel processing paradigm comes many challenges for efficiently interconnecting tens to hundreds of cores on a chip and possibly many thousands of chips in stand-alone or distributed systems. To meet the challenges, on-chip network (or NoC) communication architectures must be developed that provide scalable performance while both requiring minimal resources and consuming ultra-low power. This research investigates cross-cutting approaches and techniques to enhance on-chip network power, performance, and resource efficiency in CMP systems. Architecture-level support is explored for effectively exploiting circuit-level power-gating techniques. The objective is to maximize static power savings and minimize performance penalty of the NoC while conserving overall system dynamic power and energy expenditure when applying the techniques. Innovative approaches for minimizing NoC resources and enabling flexibility in resource utilization are also explored. The objective is to improve NoC resource efficiency while balancing system-level tradeoffs. The research plan establishes a systematic, comprehensive, and empirically-based method of investigating efficient communication architectures for many-core CMP systems, soundly grounded by theoretical support, that will lead to the design of promising new approaches and techniques. Beyond its contribution to fundamental advancements in computing, this research has broader potential impact to society through its outreach activities to broaden participation in computing and workforce development of persons from diverse backgrounds.