EAGER: Reconfigurable Network Hardware for Message-Driven Systems

消息传递一直被认为是构建并行和分布式计算的强大工具。30多年前的系统都是围绕消息传递构建的，并将其作为基本的进程间通信原语。然而，由于消息传递的开销，消息传递的使用仅限于相对粗粒度的应用程序体系结构。该项目提供硬件来支持将可编程网络接口（10gbps netfpga）耦合到进程调度中的初始演示，以支持细粒度消息传递。该项目探索了基于未来概念的消息驱动计算的新型硬件和软件支持，这是一个来自编程语言近40年的概念。它还建立在NetFPGA平台和PCI-E总线和处理器（如最新的Intel Xeon E5系列处理器）提供的内存模型上。使用对锁和事务性内存的硬件支持以及Data-Direct I/O到缓存中，结合基于未来的进程执行模型，这种未来和消息驱动调度的新方法在一个现实的框架中重新审视了强大的历史方法，如数据流，该框架将对高性能并行计算和可扩展的网络服务体系结构产生影响。

Message passing has long been known as a powerful tool for structuring parallel and distributed computation. Systems dating back more than 30 years have been built around message passing as the fundamental interprocess communications primitive. However, the use of message passing has been restricted to relatively coarse-grained application architectures due to message passing overhead. This project provides hardware to support an initial demonstration of coupling programmable network interfaces (10 Gbps NetFPGAs) into process scheduling in support of fine-grained message passing.The project explores novel hardware and software support for message-driven computation based on the concept of futures, a nearly 40 year old concept from programming languages. It also builds on both the NetFPGA platform and the memory models made available by the PCI-E bus and processors such as the latest Intel Xeon E5 series processors. Using the hardware support for locks and transactional memory as well as Data-Direct I/O into the cache in combination with a process execution model based on futures, this new approach to futures and message-driven scheduling revisits powerful historical approaches like dataflow in a realistic framework that stands to have impact in high-performance parallel computing and scalable network service architectures.