STARSS: Small: GC@Scale: Synthesis, optimization, and implementation of Garbled Circuits for Scalable Privacy-Preserving Computing

对敏感数据进行计算是几个现代世界应用程序的核心问题。安全函数评估(SFE)允许不信任的各方在其私有输入上联合计算任意函数，而不会透露除结果以外的任何内容。GC@Scale项目专注于解决SFE的新的可扩展方法，这些方法直接转化为更强大的加密和安全性，适用于具有敏感数据的无数任务。这些应用范围很广，包括对医疗、基因组和生物特征数据的隐私保护处理，以及个人、政府和工业云计算。该项目包括一个雄心勃勃的教育项目，面向本科生和研究生，还解决了与出轨相关的问题。使用乱码电路(GC)的SFE的概念是由姚提出的。尽管对GC实现进行了十年的研究，并取得了一些关键进展，但现有方法的可扩展性受到了以有向无环图表示的电路表示和软件级局部逻辑优化的阻碍。GC@Scale利用了Pi最近的工作，通过将GC生成视为非典型的时序逻辑合成，改变了SFE的格局。该项目计划促进对超临界流体萃取方法的理解和扩大探索，同时丰富逻辑设计、综合、映射和优化的理论、实践和工具。提出的计划包括：(I)设计和实现用于安全计算的高效通用乱码处理器；(Ii)创建具有挑战性的特定于应用的GC匹配和搜索引擎，其线性复杂度高于线性复杂度。(Iii)为机器学习任务设计新的定制SFE引擎。

Computing on sensitive data is a standing challenge central to several modern-world applications. Secure Function Evaluation (SFE) allows mistrusting parties to jointly compute an arbitrary function on their private inputs without revealing anything but the result. The GC@Scale project focuses on novel scalable methods for addressing SFE, which directly translate to stronger cryptography and security for myriads of tasks with sensitive data. The applications are wide reaching and include privacy-preserving processing of medical, genome, and biometric data, as well as personal, government, and industrial cloud computing. The project includes an ambitious educational program that targets both undergraduate/ graduate students, and also addresses issues related to outreach.The concept of SFE using Garbled Circuits (GC) was introduced by Yao. Despite a decade of research in GC implementation and several key progresses, scalability of the available methods has been hampered by the circuit representation as a directed acyclic graph, and software-level local logic optimizations. GC@Scale leverages PI's recent work, which has changed the SFE landscape by viewing GC generation as an atypical sequential logic synthesis. The project plans to advance the understanding and enable expanded exploration of SFE methodologies, while simultaneously enriching the theory, practice, and tools for logic design, synthesis, mapping and optimization. The proposed plan includes: (i) design and FPGA implementation of an efficient general purpose Garbled Processor for secure computation; (ii) Creating the challenging application-specific GC matching and search engines with a higher than linear complexity. (iii) Devising new custom SFE engines for Machine Learning tasks.