PFI-RP: Next-Generation Microcontroller for the Era of Internet of Smart Things

这一创新-研究伙伴关系(PFI-RP)项目的更广泛影响/商业潜力是开发和商业化技术，为微控制器(一种计算机芯片)创造下一代硬件。由于物联网(IoT)、可穿戴设备、智能建筑、移动机器人、无人机等最近的趋势，基于微控制器的设备市场一直在快速增长，并有望持续下去。这个市场一直在寻找功耗非常低的微控制器硬件来延长电池寿命。这个市场还一直在寻求增加计算能力，以满足日益增长的复杂工作负载的需求，例如神经网络算法，而不会大幅增加功耗。然而，自几十年前首次开发以来，微控制器经历了相当渐进的改进，不能支持这些新出现的需求。如果提议的技术成功，将创造下一代微控制器硬件，以实现显著更高的性能、能效和稳健性，从而支持这一关键市场需求，并提出强大的价值主张。拟议的项目将进一步发展美国国家科学基金会资助的几项最新研究成果。近阈值电压和亚阈值电压(NTV，STV)技术将电源电压缩减到额定电平的一半到四分之一，被认为是降低功耗的最有效方法之一。然而，这种方法还没有被广泛接受，因为硬件在工作条件(温度)、制造工艺变化和长期器件老化的情况下很快就会失去稳定性。随着非冯-诺依曼硬件加速器和微控制器片上系统中的模拟混合信号构建块的出现，这个问题变得更加严重。该项目的目标是创造并商业化能够有效应对稳健性挑战的技术，从而实现能效和性能提高一到两个数量级。该项目的拟议工作将集中在开发适用于商用微控制器、非冯-诺伊曼神经网络加速器和模拟混合信号积木的功耗/面积高效的就地错误检测和纠正电路(EDAC)和片上集成数字电压调节器和DC-DC转换器。该项目的预期结果是集成了开发的技术的下一代微控制器硬件的硅原型，展示了极大地改进的性能、功率和坚固性。该奖项反映了NSF的法定使命，并通过使用基金会的智力优势和更广泛的影响审查标准进行评估，被认为值得支持。

The broader impact/commercial potential of this Partnerships for Innovation - Research Partnerships (PFI-RP) project is to develop and commercialize the technologies to create the next generation hardware for microcontrollers (a type of computer chip). The market of the microcontroller-based devices has been rapidly growing and expected to continue, thanks to recent trends such as the Internet of Things (IoT), wearables, smart buildings, mobile robots, drones, etc. This market has been seeking microcontroller hardware that consumes very little power to extend the battery life. This market also has been seeking to increase computing capability to meet the growing need of complex workloads, such as a neural network algorithm, without much-increasing power consumption. However, since they were first developed multiple decades ago, microcontrollers have undergone rather incremental improvements and cannot support those emerging needs. The proposed technology, if successful, will create next-generation microcontroller hardware to achieve significantly higher performance, power-efficiency, and robustness, thereby supporting this critical market demand and posing a strong value proposition. The proposed project will further develop several recent NSF-funded research results. The near- and sub-threshold voltage (NTV, STV) techniques, where the supply voltage is scaled down to a half to a quarter of the nominal level, has been considered one of the most effective ways to reduce power consumption. However, this approach has not been widely accepted because the hardware quickly loses robustness across operating conditions (temperature), manufacturing process variations, and long-term device aging. This problem becomes even worse with non-Von-Neumann hardware accelerators and analog-mixed-signal building blocks in the microcontroller system-on-chip. This project's objective is to create and commercialize the technologies that can effectively address the robustness challenge and thus achieve one to two orders of magnitude better power-efficiency and performance. The proposed effort in this project will be centered on creating power/area-efficient in-situ error detection and correction circuits (EDAC) and on-chip integrated digital voltage regulators and DC-DC converters that are applicable for commercial microcontrollers, non-Von-Neumann neural-network accelerators, and analog-mixed-signal building blocks. The anticipated result of the project is the silicon prototype of the next-generation microcontroller hardware integrating the developed technologies, demonstrating largely improved performance, power, and robustness.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.