SBIR Phase II: Next Generation High Performance EUV Photomasks.

该小型企业创新研究（SBIR）第二阶段项目的更广泛影响/商业潜力是通过制造7纳米及更小的集成电路（IC）来推动下一代先进计算能力和性能。今天的中央处理器（CPU）包含7.2个B芯片，每年生产超过1.2个六次方芯片。下一代技术预计将通过传统计算和潜在的新范式来实现人工智能和机器学习，用于自动驾驶汽车和智能建筑等变革性应用，但需要新的方法来制造合适的芯片。 拟议中的项目将开发一种技术来满足这一需求，因为芯片制造商满足了他们的预期目标。拟议项目解决了与光刻工具及其组件的7 nm节点大批量制造相关的挑战。EUV光掩模是一种高商品组件，将集成电路设计图案化并复制到硅晶片中。目前的EUV光掩模具有约65%的次优制造产率，并且在其架构的制造期间遭受缺陷。在操作使用期间，光掩模受到EUV等离子体光源产生的碎片的损坏，这些碎片注入掩模中并不可避免地在晶片中复制，从而破坏集成芯片图案。在大批量制造中，这些问题表现在晶圆产量、掩模的可重用性上，并推动了对高成本实时检测和计量的需求。我们提出了一种新的EUV光掩模，它保证了更高的鲁棒性缺陷，更高的制造产量，更好的均匀性和更多的可重复使用的掩模在操作和更长的寿命。该项目的目标是评估EUV掩模设计的新集成架构，开发更高产量的制造工艺并表征其EUV性能。更强大的架构减少了现场计量和检测的资本支出要求，并最终降低了下一代电子产品的成本。该奖项反映了NSF的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase II project is to drive the next generation of advanced computing power and performance by manufacturing integrated circuits (ICs) at 7 nm and smaller. Today's central processing units (CPUs) contain 7.2 B chips and over 1.2 sextillion chips are manufactured per year. Next generation technology is expected to enable artificial intelligence and machine learning through both conventional computing and potentially new paradigms for transformative applications such as self-driving cars and smart buildings, but new ways are needed to make appropriate chips. The proposed project will develop a technology to address this need as chipmakers meet their desired goals. The proposed project addresses challenges related to high volume manufacturing at the 7 nm node for lithography tools and their components. An EUV photomask, a high commodity component, patterns and replicates integrated circuit design into silicon wafers. Current EUV photomasks have a sub-optimal manufacturing yield of ~65% and suffer from defectivity during fabrication of its architecture. During operational use the photomask sustains damage from the debris generated by the EUV plasma light source that implants in the mask and inevitably replicates in the wafer, destroying the integrated chip pattern. In high volume manufacturing, these issues manifest in the wafer yield, the reusability of a mask, and drive the need for high cost real-time inspection and metrology. We propose a new EUV photomask which promises a higher robustness to defects, a higher manufacturing yield, better uniformity and more reusability of masks in operations and longer lifetime. The goals of the project are to evaluate new integrated architecture for the EUV mask design, develop a higher yield fabrication process and characterize their EUV performance. More robust architectures reduce capital outlay requirements for in-situ metrology and inspection and ultimately bring down the cost of next generation electronics.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.