CAREER: Regulator-Gating (ReGa): A New On-Chip Power Delivery Architecture

随着半导体行业的不断进步，特征尺寸小于20 nm的晶体管已经能够在单个芯片上集成数十亿个晶体管。很大一部分电路块在任何给定时间处于非活动状态或处于降低功率状态，以满足功率和热约束。这种利用墙促使半导体界在芯片面积和电路速度之间做出妥协，以降低整体功耗。尽管有大量的研究和对整体功率优化技术的日益增长的需求，但是现有的最小化功率消耗的努力通常是不连贯的，并且被分成两部分：i)负载电路的动态和静态功率损失被最小化，或者ii)功率转换期间的功率损失被最小化。因此，在现代移动平台中，超过32%的总功率在高到低电压转换过程中甚至在到达负载电路之前就被消耗掉了。无论是PI的前期工作，还是之前的研究，都没有提出一种全面的方法来设计和管理分布式片上功率传输，并且在获得高总电压转换效率和热感知设计方面的应用有限。本项目的最终目标是重新审视并从根本上定制片上功率传输基础设施的设计和管理。与以充分利用整个芯片面积为目标设计电力网络的传统方案相比，拟议的研究将提供一种自适应电力输送基础设施，该基础设施可在充分利用和未充分利用的操作模式下提供高电压转换效率。将提出新的电压调节技术和支持电路，电力输送网络的物理设计，以及电力管理方案。重点将放在并行电压调节和交付上，其中各个调节器的分配、大小和类型是协同优化的，考虑到各种可能的权衡。稳压门控将专门用于：i)迫使各个电压调整器在其最省电的区域运行，ii)传播引起局部热点的集中热量，以及iii)打开靠近有源电路的电压调整器以降低噪声。该项目的研究部分对半导体相关研究的所有子领域都有广泛的影响，因为功率效率已成为主要的瓶颈。该项目的教育部分将提供指导方针，说明如何将不同的教学技术整合到本科生和研究生课程中，以加强工程教育。PI将促进女性和代表不足的少数族裔参与STEM领域，并与当地一所历史上一直是黑人的大学建立牢固的联系，以增加南佛罗里达大学电气工程系代表不足的少数族裔的入学人数。

With continuous advancements in the semiconductor industry, transistors with smaller than 20 nm feature size have enabled the integration of multi-billion transistors on a single die. A large proportion of the circuit blocks is either inactive or in a reduced-power state at any given time to satisfy the power and thermal constraints. This utilization wall has urged the semiconductor community to compromise the chip area and the speed of the circuit to reduce the overall power consumption. Despite the significant amount of research and growing necessity for a holistic power optimization technique, existing efforts to minimize power dissipation are typically not coherent and are disjointed into two pieces: i) the dynamic and static power loss at the load circuits is minimized or ii) the power loss during power-conversion is minimized. As a result, more than 32% of the overall power is dissipated during high-to-low voltage conversion before even reaching the load circuits in modern mobile platforms. Neither the preliminary works of the PI nor the previous studies present a holistic approach for the design and management of distributed on-chip power delivery and are of limited use to attain high overall voltage conversion efficiency and thermal-aware design.The ultimate goal of this project is to revisit and fundamentally tailor the design and management of on-chip power delivery infrastructure. As compared to the conventional schemes where the power network is designed targeting the full utilization of the overall chip area, the proposed research will provide an adaptive power delivery infrastructure that is tailored to provide high voltage conversion efficiency during both fully-utilized and under-utilized modes of operation. Novel voltage regulation techniques and support circuits, physical design of power delivery networks, and power management schemes will be proposed. Specific emphasis will be placed on parallel voltage regulation and delivery where the allocation, size, and type of individual regulators are optimized synergistically considering various possible tradeoffs. Regulator-gating will be used specifically to: i) force individual voltage regulators to operate in their most power-efficient region, ii) spread the concentrated heat that causes local hotspots, and iii) turn on the voltage regulators close to the active circuits to reduce noise. The research component of this project has broad implications across all sub-areas of semiconductor-related research as power efficiency has become the primary bottleneck. The education component of this project will provide guidelines on how different teaching techniques can be integrated in undergraduate and graduate level courses to enhance the engineering education. The PI will promote the participation of women and underrepresented minorities in STEM fields and build strong ties with a local historically black college to increase the enrollment of underrepresented minorities at the University of South Florida's Electrical Engineering Department.