SHF: Small: EVE: Ephemeral Vector Engines

数据并行内核在各种各样的要求苛刻的应用领域（包括图形渲染、计算机视觉、音频处理、物理仿真、机器学习和图形处理）中占主导地位。由于不再可能依靠技术扩展来实现晶体管性能和能效的不可避免的改进，因此与通用处理器相比，对于具有大量数据级并行性（DLP）的代码，对专用硬件重新产生了兴趣，以提高性能和效率。不幸的是，当这些计算系统正在执行许多其他缺乏DLP的有趣工作负载时，这种专用硬件处于空闲状态。该项目正在探索一种新的方法，能够通过重新配置现代计算机系统中已经包含的内存来“按需”创建专门的硬件，以处理存储和计算。该项目的广泛意义和重要性源于计算机架构师需要创造性地减轻摩尔定律即将结束所带来的挑战，以及软件/硬件协同设计方法的潜在变革影响。利用DLP的两种流行的硬件加速器风格包括数据并行加速（DPA），其专注于将主内存中的数据移动到计算硬件，以及内存处理（PIM），它专注于将计算硬件移动到内存中的数据。内存中的原位处理（PIM）是最近提出的一种方法，它试图显着减少与利用数据级并行性相关的面积开销，同时获得大部分的好处。原位PIM使用位线计算来在传统存储器阵列的单次读取中执行基本逐位逻辑运算。通过在外围电路中添加额外的逻辑、多路复用和状态元素，每个存储器列可以进一步转换成位串行ALU。这个项目对以前的工作进行了两个关键的观察：（1）原位PIM缺乏令人信服的编程模型;（2）原位PIM需要大量的并行性来超过位串行执行开销。这个项目正在探索短暂向量引擎（EVE）作为解决这些挑战的新方法。EVE使得能够动态地重新利用一个或多个私有L2高速缓存通路以用作按需（即，短暂的）向量引擎，其使用新颖的可重新配置的位串行/位并行原位处理在SRAM中实现。EVE支持未经修改的RISC-V向量指令集，并且可以快速重新配置为使用位串行或位并行执行。位串行执行提供更高的吞吐量但更长的延迟，而位并行执行提供更低的吞吐量但更短的延迟。该项目采用垂直集成的研究方法，跨越电路，微架构，架构和应用程序，探索三个研究方向。推力1：EVE电路正在探索如何在SRAM阵列的外围实现可重配置的位串行/位并行计算逻辑，以最大限度地减少面积，能量和时序开销。目标2：EVE微架构正在探索如何有效地将高级向量指令映射到低级微操作。推力3：EVE Architecture正在探索如何将EVE微架构集成到一个完整的系统中，通过常规DLP加速应用程序，同时为没有常规DLP的应用程序增加很少或没有的面积，能源和性能开销。该项目还在追求两个更广泛的影响计划。第一个项目是为高中女生组织为期一周的计算机工程设计体验活动，这是一项雄心勃勃但具体的努力，旨在增加妇女对计算机工程的参与。第二个奖项是通过将开源CAD工具和新兴的PIM建筑方法整合到本科生和研究生课程中，为康奈尔大学毕业生更好地为后摩尔定律时代做好准备的举措。该奖项反映了NSF的法定使命，并通过使用基金会的智力价值和更广泛的影响审查标准进行评估，被认为值得支持。

Data-parallel kernels dominate the computational workload in a wide variety of demanding application domains, including graphics rendering, computer vision, audio processing, physical simulation, machine learning, and graph processing. Since it is no longer possible to rely on technology scaling for inevitable improvements in transistor performance and energy efficiency, there is renewed interest in specialized hardware to improve performance and efficiency compared to general-purpose processors for codes with significant amounts of data-level parallelism (DLP). Unfortunately, this specialized hardware lies idle when these computing systems are executing the many other interesting workloads that lack DLP. This project is exploring a new approach that is able to create specialized hardware "on-demand" by reconfiguring the memory already contained within modern computer systems to handle both storage and computation. The project's broader significance and importance are rooted in the need for computer architects to creatively mitigate the challenges imposed by the looming end of Moore's law, and the potential transformative impact of a software/hardware co-design approach.Two popular styles of hardware accelerators for exploiting DLP include data-parallel acceleration (DPA), which focuses on moving data in main memory to the compute hardware, and processing-in-memory (PIM), which focuses on moving compute hardware to the data in memory. In-situ processing-in-memory (PIM) is a recently proposed approach that attempts to significantly reduce the area overhead associated with exploiting data-level parallelism while at the same time reaping most of the benefit. In-situ PIM uses bit-line computation to perform basic bit-wise logical operations in a single read of a traditional memory array. Each memory column can be further transformed into a bit-serial ALU by adding extra logic, multiplexing, and state elements in the peripheral circuitry. This project makes two key observations about prior work on in-situ PIM: (1) in-situ PIM lacks compelling programming models; and (2) in-situ PIM requires massive parallelism to outweigh bit-serial execution overheads.This project is exploring ephemeral vector engines (EVE) as a new approach to address these challenges. EVE enables dynamically repurposing one or more private L2 cache ways to serve as on-demand (i.e., ephemeral) vector engines implemented using a novel reconfigurable bit-serial/bit-parallel in-situ processing-in-SRAM. EVE supports the unmodified RISC-V vector instruction set and can be rapidly reconfigured to use either bit-serial or bit-parallel execution. Bit-serial execution provides higher throughput but longer latencies, while bit-parallel execution provides lower throughput but shorter latencies. This project is using a vertically integrated research methodology spanning circuits, microarchitecture, architecture, and applications to explore three research thrusts. Thrust 1: EVE Circuits is exploring how to implement reconfigurable bit-serial/bit-parallel compute logic in the periphery of the SRAM array so as to minimize area, energy, and timing overhead. Thrust 2: EVE Microarchitecture is exploring how to efficiently map higher-level vector instructions into lower-level micro-operations. Thrust 3: EVE Architecture is exploring how to integrate the EVE microarchitecture into a complete system accelerating applications with regular DLP, while adding little to no area, energy, performance overhead for applications without regular DLP.This project is also pursuing two broader impact initiatives. The first is an ambitious yet concrete effort to increase participation of women in computer engineering by organizing a week-long computer engineering design experience for high-school girls. The second is an initiative to better preparing Cornell graduates for the post-Moore's law era, by integrating open-source CAD tools and the emerging PIM architectural approach into the undergraduate and graduate curriculum.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.