Collaborative Research: SHF: Small: Tangram: Scaling into the Exascale Era with Reconfigurable Aggregated "Virtual Chips"

由于技术扩展的限制，通用处理器的设计正在达到性能瓶颈。基于芯片的系统通过在一个封装内集成小芯片（芯片）提供了一种有前途的解决方案。小芯片还支持离散芯片架构的异构集成，例如CPU、GPU、DSP和FPGA。然而，高性能的基于芯片的系统的设计面临着严峻的挑战：芯片间的通信是一个关键的瓶颈;资源需要在芯片之间有效地共享，以提高性能成本比;功率和热管理需要优化，以更好地在封装集成。因此，这种设计需要采取更全面的方法，并需要调查跨处理节点，存储和互连结构的交叉问题。本研究提出从异质聚合芯片构建“虚拟芯片”，使系统不仅可以获得单片超级芯片的性能优势，而且还可以打破可扩展性瓶颈。该项目的一个主要成果将是一套优化方法，使可重构架构的设计，利用混合无线互连无缝连接计算和存储组件。为此，研究目标包括：（1）设计可重构的体系结构，打破小芯片的边界，实现高效的资源共享;（2）开发模型，量化应用程序和硬件资源之间的交互，以快速设计空间探索;（三）设计混合无线互连网络，以无缝地桥接小芯片之间的物理间隙，并通过本研究的目的是在硬件架构、网络和设备等多个设计层次之间架起差距座桥梁。由于其跨领域的性质，拟议的研究有可能改变高性能，节能和成本效益的系统，能够满足新兴应用的需求与不断增长的带宽和性能需求的设计。 这项研究的教育贡献包括将研究与教学和培训相结合，设计专注于未来工程师培训的教程和研讨会，以及与行业互动以加速技术转让。通过作为拟议项目一部分的外展活动，将吸引更多的本科生和少数民族学生进入这一工程领域。该奖项反映了NSF的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

The design of general-purpose processors is reaching a performance bottleneck due to the limitations in technology scaling. Chiplet-based systems offer a promising solution by integrating small dies (chiplets) inside one package. Chiplets also enable heterogeneous integration of discrete chip architectures, such as CPUs, GPUs, DSPs, and FPGAs. However, the design of high-performance chiplet-based systems faces serious challenges: inter-chiplet communication is a critical bottleneck; resource needs to be efficiently shared among the chiplets to improve the performance-cost ratio; power and thermal management need to be optimized for better in-package integration. Consequently, such designs need to take a more holistic approach, and investigations are needed on the cross-cutting issues across the processing nodes, storage and interconnection fabric. This research proposes to build "virtual chips" from heterogeneous aggregated chiplets, so that the system can not only reap the performance benefit of a monolithic super chip but also break the scalability bottleneck. A major outcome of the project will be a set of optimization methods that enable the design of a reconfigurable architecture, leveraging a hybrid wireless interconnection to seamlessly connect the computing and memory components. To this end, the research goals include: (1) design of reconfigurable architectures to break the chiplet boundaries for efficient resource sharing; (2) development of models to quantify interactions between the applications and hardware resources for fast design-space exploration; (3) design of a hybrid wireless interconnection network to seamlessly bridge the physical gaps between chiplets and enable reconfigurable architectures through the flexibility of wireless networks; and (4) design of novel wireless antennas to improve energy and thermal efficiency.The proposed research bridges the gap between multiple layers of the design stack: hardware architectures, networks and devices. Due to its cross-cutting nature, the proposed research has the potential to transform the design of high-performance, energy-efficient and cost-effective systems that are able to meet the demand of emerging applications with growing bandwidth and performance needs. The educational contributions of this research include integrating research with teaching and training, design of tutorials and workshops focusing on the training of future engineers, and interaction with industry to accelerate technology transfer. Through the outreach activities as part of the proposed project, more undergraduate and minority students will be attracted to this field of engineering.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.