An Energy-Efficient, CMOS-based, and Scalable Mixed-Signal DNN System with Reconfigurable Crossbars

深度神经网络在广泛的应用中表现出了高精度，这些应用通常在云上实现。然而，有必要使计算接近数据源，以解决数据隐私，系统延迟和能耗问题，这些问题在医疗保健，自动驾驶汽车和物联网等应用中至关重要。另一个出现的问题涉及数字系统的典型使用来执行必要的计算，但数字系统在有效处理大数据方面受到根本限制。虽然模拟计算作为一种有前途的替代方案出现，它可以在能源效率和计算速度上超过其数字对应物几个数量级，但这种替代方案面临着许多挑战。首先，新兴的模拟存储器是不可靠的，不成熟的，与标准的CMOS技术不兼容。其次，设计可定制和可扩展的模拟深度神经网络，以支持广泛的深度神经网络比数字对应更难，导致更长的设计周期和更高的成本。该项目的广泛目标是通过在存储器技术，电路，架构和系统级别的模拟和数字设计中使用创新的研究方向来应对这些挑战，从而为各种应用提供高可扩展性和极大的灵活性。该项目将首先开发一种具有新型可重构架构和新存储器技术的专用电子芯片，利用软件-硬件协同设计方法来实现必要的优化。随后，该项目将利用多个此类芯片构建一个可扩展的系统，以适应更大的神经网络的需求。该项目可能会影响未来硬件加速器的设计，因为它提高了能源效率，提高了计算速度，丰富了深度神经网络的功能，同时释放了模拟计算的新功能，并允许大规模部署边缘设备。教育方面包括填补与深度神经网络硬件实现相关的电气和计算机工程课程的差距，并为参与的学生提供各种技能，重点关注少数民族和代表性不足的群体。广泛的推广活动包括为底特律大都会的K-12学生开发和教授两门以项目为导向的机器学习和电路设计暑期课程。 该项目在技术、电路、架构和系统层面提出了多项创新。在存储器技术层面，我们提出了一种新的，基于CMOS的，模拟多稳态存储器电路，提供了与交叉系统的兼容性，提供了一个模拟的解决方案来存储的权重，并执行本地计算在一个高度并行和节能的方式。在电路级，我们提出了一个本地存储和处理单元，它采用建议的模拟存储器执行乘法和累加操作，只利用一个存储器单元，以支持正负权重。在体系结构层次，我们提出了一种新的可重构体系结构，以构建一个可扩展和高度可定制的推理机。在这种架构中，交叉开关单元可以使用开关矩阵电路水平和/或垂直扩展，从而与固定大小和分离的交叉开关阵列相比，提高了利用率并降低了功耗。此外，我们建议使用可重新配置的数模转换器和模数转换器池，这些转换器非常适合可重新配置的架构，并将为每个深度神经网络层优化其位分辨率。此外，所提出的推理引擎采用低功耗开源处理器（特别是RISC-V），以实现高灵活性并提供各种功能，包括管理层之间的数据流，配置和校准。为了最大限度地减少读取/解码能耗，将开发定制数字电路以支持非线性和池化功能。考虑到工艺变化，我们将利用内置自测试和内置自校准技术来测试和校准所有的模拟电路，利用片内电路和配置寄存器。最后，在系统级，多个芯片将通过PCI Express互连，以支持更大的模型。该奖项反映了NSF的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

Deep neural networks have demonstrated high accuracy in a broad spectrum of applications, which are typically implemented on the cloud. However, it has become necessary to bring computation close to the data sources to address the data privacy, system latency, and energy consumption concerns, which are critical in applications such as healthcare, autonomous vehicles, and Internet-of-Things. Another arising issue relates to the typical use of digital systems to perform the necessary computations, but digital systems are fundamentally limited in handling big data efficiently. Although analog computation emerged as a promising alternative, which can outperform its digital counterpart by several orders of magnitudes in energy efficiency and computational speed, this alternative faces many challenges. First, emerging analog memories are unreliable, immature, and incompatible with standard CMOS technologies. Second, designing customizable and scalable analog deep neural networks that can support a broad range of deep neural networks is harder than the digital counterpart, leading to longer design cycles and higher costs. The broad goal of this project is to address these challenges by using innovative research directions in both analog and digital designs at the memory technology, circuit, architecture, and system levels, thereby enabling high scalability and great flexibility for various applications. This project will first develop a specialized electronic chip with a novel reconfigurable architecture and a new memory technology, utilizing a software-hardware co-design approach to achieve the necessary optimizations. Subsequently, this project will build a scalable system utilizing multiple such chips to adapt to the needs of even larger neural networks. This project will likely impact the design of future hardware accelerators because it improves energy efficiency, enhances computational speed, and enriches the functionality of deep neural networks while unlocking new capabilities of analog computations and allowing a massive deployment of edge devices. The educational aspects include filling the gap in the electrical and computer engineering curriculum related to deep neural network hardware implementation and providing various skills to participating students, focusing on minority and underrepresented groups. The extensive outreach activities include developing and teaching two summer project-oriented courses in machine learning and circuit design for K-12 students in metro Detroit. This project proposes multiple innovations at the technology, circuit, architecture, and system levels. At the memory technology level, we propose a new, CMOS-based, analog multi-stable memory circuit that offers compatibility with crossbar systems, provides an analog solution to store the weights, and performs local computations in a highly parallel and energy-efficient manner. At the circuit level, we propose a local storage and processing unit, which employs the proposed analog memory to perform multiply-and-accumulate operations, utilizing only one memory unit to support both positive and negative weights. At the architecture level, we propose a novel reconfigurable architecture to construct a scalable and highly customizable inference engine. In this architecture, crossbar cells can be expanded horizontally and/or vertically using switch matrix circuits, thereby improving the utilization and reducing the power consumption compared to the fixed-size and separate crossbar arrays. Moreover, we propose the usage of a pool of reconfigurable digital-to-analog converters and analog-to-digital converters, which are well suited for the reconfigurable architecture, and will optimize their bit resolutions for each deep neural network layer. Furthermore, the proposed inference engine employs a low-power open-source processor (specifically RISC-V) to enable high flexibility and provide various functions, including the management of the data flow between layers, configuration, and calibration. To minimize the fetch/decode energy consumption, custom digital circuits will be developed to support non-linear and pooling functions. To account for process variations, we will exploit built-in-self-test and built-in-self-calibration techniques to test and calibrate all the analog circuits, utilizing on-chip circuits and configuration registers. Finally, at the system level, multiple chips will be interconnected through PCI Express to support larger models.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.