GOALI: ASCENT: Wafer-Scale Computational System (WaSCoS) with heterogeneous integration, power-heat transport, and optical interconnects

晶圆级系统有可能将一个机架的电子设备浓缩到一个晶圆上，同时碳足迹要低得多。本提案旨在探索和展示使这一潜力成为现实所需的技术。关注的主要技术将是细间距异质集成，其中大量非常小且多样（即异质）的电子部件（所谓的芯片或dieelets）紧密地互连在一起；芯片之间的连接数量大约是当今传统系统的10到100倍。这两个特性可以大大减少系统的内存占用。传统的印刷电路板将被大型硅片所取代，粗糙的焊接连接将被密度提高10到100倍的微观无焊焊接连接所取代。这种系统的紧凑特性意味着需要在更小的空间内输送更多的能量，并且需要从更小的空间中提取更多的热量。该系统可能实现的巨大计算密度需要使用精密微对准光纤与高密度电连接器相结合的新方法将数据移入和移出系统。这项技术将在芯片的摩尔定律失效的地方起飞，并允许计算能力的可持续扩展。这些技术的发展也将为我们的学生提供一个有价值和实用的学习工具，这将是包装和半导体技术制造业复苏计划所需要的，也将流入现有的外展项目，以吸引加州大学洛杉矶分校教师组织的高中生进入STEM领域。该项目旨在生产一种系统，其中在Si-IF上组装的模具间距低于10 μm（与传统印刷电路板上的500 μm球栅阵列（BGA）间距相比）。Si-IF上的布线间距为亚μm，而使用精密对准热压缩键合的PCB通常为数十μm。这使得异质芯片（处理器、存储器、通信芯片等）的封装具有非常高的带宽、低延迟和低每比特能量——远远超出了当今最先进的硅中间层封装方法的指标。理想情况下，这种方法将允许接近10tb的统一可访问内存，其平分带宽比目前的系统大近75倍，总带宽增加约250倍，统一延迟减少约40倍。这样的结果可以支持前所未有的计算工作负载。除了模具装配之外，实现这一目标的挑战还包括综合这样一个系统所需的架构和设计基础设施；电力输送和散热解决方案既能提供这样一个系统所需的25千瓦的预计功率，又能安全有效地提取类似的热量；以及能够传输高达20-100 Tb/s数据的波分复用方法，同时使用名为“FlexTrate”的灵活扇出晶圆级封装方法，符合足够小的外形尺寸。“这个奖项反映了国家科学基金会的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

Wafer-scale systems have the potential to condense a rack's worth of electronics into a single wafer along with a much lower carbon footprint. This proposal seeks to explore and demonstrate technologies needed to make this potential a reality. The main technology of concern will be fine-pitch heterogeneous integration, wherein a great number of very small and diverse (i.e. heterogeneous) electronic parts (so-called chiplets or dielets) are interconnected very closely together; the number of connections between the chips is about 10 to 100 times more than today’s conventional systems. These two features allow for shrinking the footprint of the system considerably. Traditional printed circuit boards are replaced by large silicon wafers and coarse soldered connections will be replaced by microscopic solderless welded connections that are 10 to 100 times denser. The compact nature of such systems means that more power needs to be delivered in a smaller space and more heat needs to be extracted from a smaller space. The immense computing density possible with this system requires new methods of moving data in and out of the system using precision micro-aligned optical fibers combined with high density electrical connectors. This technology will take off where Moore’s law for chips leaves off and allow for sustainable scaling of computing capabilities. The development of these technologies will also provide a valuable and practical learning vehicle for our students that will be needed for the manufacturing resurgence that is planned for packaging and semiconductor technology and will also flow into existing outreach programs to attract high school students organized by UCLA faculty to STEM fields.The project aims to produce a system wherein dies are assembled on Si-IF to pitches of sub-10-μm (compared to 500-μm ball grid array (BGA) pitches on a traditional printed circuit board). The wiring pitch on the Si-IF will be sub-μm, compared to the tens of μm typically seen on a PCB using precision aligned thermal compression bonding. This permits the packaging of heterogeneous dielets (processors, memory, communication chips, etc.) with very high bandwidth, low latency, and low energy per bit - well beyond the metrics of even the most advanced silicon interposer packaging approaches today. Ideally, such an approach will allow near 10-TB of uniformly accessible memory with bisection bandwidths near 75x larger than today’s systems, an aggregate bandwidth increase of about 250x and a uniform latency reduction of about 40x. Such results could support unprecedented workloads in computing. Aside from die assembly, challenges to this goal include architecture and design infrastructure needs for synthesizing such a system; power delivery and thermal dissipation solutions able to both provide the projected  25-kW required by such a system and safely and efficiently extract a similar amount in heat; and wavelength division multiplexing approaches capable of delivering up to 20-100 Tb/s of data while conforming to a sufficiently small form factor using a flexible fan-out wafer-level packaging approach titled "FlexTrate."This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.