SHF: Small: Taming Huge Page Problems for Memory Bulk Operations Using a Hardware/Software Co-Design Approach
SHF: Small: Taming Huge Page Problems for Memory Bulk Operations Using a Hardware/Software Co-Design Approach
批准号:
2400014
负责人:
Jun Wang
金额:
$40.0万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2024
资助国家:
美国
项目状态:
未结题
起止时间:
2024-07-01 至 2027-06-30
中文摘要
与传统的动态随机存取存储器(DRAM)相比,非易失性存储器(NVM)技术的最新进展有望显著提高容量。当今的计算机通常将NVM与DRAM结合起来,构建统一的主存架构,以满足许多新兴大数据和人工智能应用的极高要求。然而,管理超高容量存储器带来了令人生畏的系统挑战。特别是,NVM驱动器的大规模并行性采用了巨大的2兆字节甚至更大的内存页。该项目的成功完成将是加速安全非易失性存储器体系结构的重要一步,其性能将得到数量级的提高。该项目还将通过吸纳西班牙裔服务机构中代表性不足的群体,以及传播计算机科学和工程教育与培训方面的研究成果,为社会做出贡献。该研究项目使用硬件和软件协同设计方法来解决这些问题。在这个项目中,将设计、建模和实现一个通用的、细粒度的内存管理系统,以显着提高单级、DRAM与超低延迟、非易失性内存架构的速度和带宽,用于中央处理单元(CPU)和图形处理单元(GPU)机器,特别是对于巨大的页面配置。利用现有硬件架构单元中未使用和过度配置的部分,通过非侵入式和侵入式两种方式实现细粒度的内存管理,实现Copy-on-Write机制的高效率和有效性。将进一步研究几个新的写时复制用例,包括检查点和快照,以及大型语言模型服务。此外,新的内存架构将与大数据管理、人工智能程序和硬件安全机器的高速处理工作流集成。该奖项反映了美国国家科学基金会的法定使命,并通过使用基金会的知识价值和更广泛的影响审查标准进行评估,被认为值得支持。
英文摘要
Recent advances in non-volatile memory (NVM) technologies promise significantly higher capacities compared to traditional dynamic random-access memory (DRAM). Today’s computers often combine NVM with DRAM to construct a unified main memory architecture that meets the extremely high demand of many emerging big data and artificial intelligence applications. However, managing ultra-high capacity memories introduces daunting systems challenges. In particular, the massive parallelism of NVM drives adoption of huge two megabytes or even larger memory pages. The successful completion of this project's activity will be a significant step towards accelerating the secure non-volatile memory architectures by orders of magnitude performance improvement. This project will also contribute to society through engaging under-represented groups from a Hispanic Serving Institution and research dissemination for computer science and engineering education and training.The research project tackles these issues using a hardware and software co-design methodology. In this project, a general-purpose, fine-grained memory management system will be designed, modeled, and implemented to significantly improve both the speed and bandwidth of single-level, DRAM combined with ultra-low latency, non-volatile memory architecture for both central processing unit (CPU) and graphic processing unit (GPU) machines, in particular for huge page configurations. The unused and overprovisioned parts of existing hardware architecture units will be exploited via both non-intrusive and intrusive ways to enable fine-granularity memory management, and achieve high efficiency and effectiveness of the Copy-on-Write mechanism. Several new Copy-on-Write use cases, including the checkpointing and snapshot, and large language model serving will be further studied. Furthermore, the new memory architecture will be integrated with the high-speed processing workflow of big data management, artificial intelligence programs, and hardware security machines.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
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