Architecture and Compiler of the High-Performance Reconfigurable Processor (HiPReP)

在高性能计算(HPC)领域，并行处理器体系结构(多核和多核处理器以及图形处理单元-GPU)在过去几年中得到了越来越多的使用，因为更高的时钟频率无法再实现性能提升。然而，这些基于许多单处理器内核的解决方案具有较大的芯片面积和较高的功耗。另一方面，现场可编程门阵列(现场可编程门阵列)形式的可编程硬件也可用于高性能计算机应用，因为现场可编程门阵列允许大规模并行处理，而无需完整处理器内核的开销。但在大多数HPC应用程序中，处理浮点数据在FPGA上是有问题的。通过组合更简单的组件，只能在一个FPGA上实现有限数量的浮点单元(FPU)。同样的限制也适用于粗粒度可重构数组(CGRA)，与FPGA相反，粗粒度可重构数组基于数据字(例如32位字)的处理单元。这使得它们在原则上更适合执行数值算法。但到目前为止，几乎所有开发的CGRA都只包含处理整数或定点数据的单元。由浮点处理器扩展的CGRA对于计算密集型算法来说是一个很有前途的选择，例如在科学计算或3D图形领域。这一延期将在这个拟议的三年项目中进行研究和评估。首先，选择合适的HPC基准程序内核并进行分析。新的CGRA将针对这些内核进行优化。在第二个工作包中，将确定参数化的HIPReP体系结构，即硬件设计，并将用SystemC语言实现仿真模型。为了有效地利用FPU的扩展，必须设计新的通信和同步机制，并且必须研究在HPC系统的存储层次中集成HIPReP模块。一名全日制博士生将主要从事这两个工作包的工作。另一名博士生计划在HIPReP上实现用于HPC应用程序的高级语言编译器原型。这是必需的，因为处理器的实际使用只能用相应的编译器来评估。为此，将开发适当的编译、调度和布局算法。最后，在项目的评估阶段将进行设计空间探索。因此，将在HiPReP处理器上模拟基准内核执行，并确定设计空间中的最优点。对于这种设计，将估计芯片实现的面积、频率和功耗。

In the area of high-performance computing (HPC) parallel processor architectures (multi- and many-core processors, and Graphics Pocessing Units - GPUs) have been increasingly used in the last few years since no performance increase could be achieved any more by higher clock frequencies. However, these solutions based on many single processor kernels come with a large chip area and a high power consumption. On the other hand, programmable hardware in the form of FPGAs (Field-Programmable Gate Arrays) is also used for HPC applications since FPGAs allow massively parallel processing without the overhead of complete processor kernels. But processing floating-point data as required in most HPC applications is problematic on FPGAs. Only a limited number of floating-point units (FPUs) can be realized on an FPGA by combining simpler components. The same limitation also holds for coarse-grained reconfigurable arrays (CGRAs) which are - as opposed to FPGAs - based on processing units for data words (e.g. 32 bit words). This makes them in principle better suited for executing numerical algorithms. But almost all CGRAs developed so far contain only units for processing integer or fixed-point data. CGRAs extended by FPUs are a promising option for computation-intensive algorithms, e.g. in the domains of scientific computing or 3D graphics. This extension will be researched and evaluated in this proposed three-year project. First, suitable HPC benchmark program kernels will be selected and analyzed. The new CGRA will be optimized for these kernels. In the second work package, the parameterized HiPReP architecture, i.e. the design of the hardware, will be determined and a simulation model in the SystemC language will be implemented. For efficiently using the extension by FPUs, novel communication and synchronization mechanisms have to be devised, and the integration of a HiPReP module in the memory hierarchy of a HPC system must be investigated. A full-time PhD student will mainly work on these two work packages. A second PhD student is planned for implementing a high-level language compiler prototype for HPC applications on HiPReP. This is required since the practical use of a processor can only be evaluated with a corresponding compiler. For this, suitable compilation, scheduling and placement algorithms will be developed. Finally, a design space exploration will be performed in the evaluation phase of the project. Therefore, the benchmark kernel executions will be simulated on the HiPReP processor, and an optimal point in the design space will be determined. For this design, the area, frequency and power consumption of a chip implementation will be estimated.