SHF: Small: Improving Memory Performance on Fused Architectures through Compiler and Runtime Innovations

SHF：小型：通过编译器和运行时创新提高融合架构的内存性能

• 批准号: 1525609
• 负责人: Xipeng Shen
• 金额: $ 47万
• 依托单位: North Carolina State University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2015
• 资助国家: 美国
• 起止时间: 2015-08-01 至 2020-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1525609&HistoricalAwards=false
• 关键词: SHF; Small; Improving; Memory; Performance

During the past decade, accelerators such as Graphics Processing Units (GPUs) have entered the area of general-purpose computing. They are now widely used for achieving high performance in scientific simulation, business analytics, image processing, and many other application domains. Their effectiveness however has been largely constrained by narrow and slow interconnections to multicore CPUs. Instead of such disjoint memories for multicore CPUs on one side and GPUs on the other, contemporary architectures are adopting an integrated design: Conventional CPUs and co-accelerators are integrated on the same die with access to the same memory. The integration provides new opportunities for synergistic execution on CPUs and GPUs, but can also intensify resource contention within the memory hierarchy. The implications yet remain to be understood.This project aims to systematically explore the new challenges and opportunities of the integration, especially for compilers and runtime systems in governing program transformations and maintaining them at runtime for data locality, task partitioning and scheduling. The PIs propose to advance the state of the art by promoting synergistic execution in support of data sharing while creating spheres of isolation between CPU and GPU execution to mitigate resource contention of non-shared data. The proposed techniques include a set of novel compiler transformations, concurrent program control and data abstractions, and systems mechanisms that fostersharing and reduce cross-boundary contention depending on memory access patterns with respect to shared hardware resources. This synergy between compiler techniques and the runtime system has the potential to significantly improve performance and power guarantees for co-scheduling program fragments on fused architectures.

在过去的十年中，诸如图形处理单元（GPU）之类的加速器已进入通用计算的区域。现在，它们被广泛用于在科学模拟，业务分析，图像处理和许多其他应用程序领域中实现高性能。然而，它们的有效性在很大程度上受到与多核CPU的狭窄和缓慢的互连的约束。当代体系结构并非一侧的多核CPU和GPU的这种不相交的记忆，而是采用了集成的设计：传统的CPU和共同加速器已集成在同一模具上，并可以访问相同的内存。该集成为CPU和GPU的协同执行提供了新的机会，但也可以加强内存层次结构中的资源争夺。该项目旨在系统地探索集成的新挑战和机遇，尤其是针对管理程序转换的编译器和运行时系统的新挑战和机会，并在运行时维护它们以进行数据区域，任务分配和调度时，尤其是对于编译器和运行时系统。 PI建议通过促进协同执行来支持数据共享，同时创建CPU和GPU执行之间的隔离领域，以减轻非共享数据的资源争论，从而推进艺术状态。提出的技术包括一组新颖的编译器转换，并发程序控制和数据摘要以及系统机制，这些机制可以根据共享硬件资源的内存访问模式来培养和减少跨边界的争论。 编译器技术与运行时系统之间的这种协同作用有可能显着提高融合体系结构的共同安排计划片段的性能和功率保证。

项目成果

T-Pack: Timed Network Security for Real Time Systems

T-Pack：实时系统的定时网络安全

• DOI: 10.1109/isorc52013.2021.00014
• 发表时间: 2021
• 期刊: IEEE International Symposium on Real-Time Computing (ISORC
• 作者: Mittal, Swastik;Mueller, Frank
• 通讯作者: Mueller, Frank