High-Performance Reliable Computing: Addressing the Parameter-Variation Challenge through a Cross-Disciplinary Architecture, CAD, and Compiler Approach

目前的半导体路线图表明，从现在开始的大约10年内，处理器芯片将集成1280亿个晶体管。不幸的是，这些非常小的晶体管将很难制造出高精度，并且容易失败。设计者面临的挑战将是如何从本质上不可靠的部件中制造出可靠、高性能、低功耗的多核芯片。原理调查者(PI)建议通过跨越体系结构、CAD和编译器领域的多学科努力来解决这些设备中参数变化的挑战。在体系结构领域，PI将开发一种新的变化引起的错误模型，一种在正常操作中容忍频繁错误的多核体系结构，以及一套减轻变化引起的错误的微体系结构技术。在CAD领域，PI将开发新的VLSI设计方法，使片上系统能够进行可感知变化的设计，包括统计时序分析、流水线重新计时、全局布线流水线和减少时钟偏差变化。最后，在软件领域，PI将开发一个动态优化框架，该框架将表征多核芯片中每个核的弱点，并通过高级调度和动态编译来塑造暴露给每个核的指令流，以减少错误频率。总体而言，PI希望在成本效益高、坚固耐用的高性能计算机方面取得根本性进展。

Current semiconductor road-maps indicate that in about 10 years from now, processor chips will integrate 128 billion transistors. Unfortunately, these very small transistors will be difficult to manufacture with high precision, and be prone to fail. The challenge for designers will be how to build reliable, high-performance, low-power multi-core chips out of components that are intrinsically unreliable and exhibit a high variability in their properties.The Principle Investigators (PIs) propose to address the challenge of parameter variation in these devices through a multidisciplinary effort that cuts across the architecture, CAD, and compiler areas. In the architecture area, the PIs will develop a novel model of variation-induced errors, a multi-core architecture that tolerates frequent errors in its normal operation, and a set of micro-architectural techniques that mitigate variation-induced errors. In the CAD area, the PIs will develop novel VLSI design methodologies that enable variation-aware design of Systems-on-Chip, including statistical timing analysis, pipeline re-timing, global wire pipelining, and clock skew variation reduction. Finally, in the software area, the PIs will develop a dynamic-optimization framework that characterizes the weakenesses of each core in a multi-core chip and shapes the instruction streams exposed to each core to reduce the frequency of errors, through advanced scheduling and dynamic compilation. Overall, the PIs hope to make fundamental advances toward cost-effective, robust high-performance computers.