Hardware/Software Cross-Layer Fault Analysis for Safe Embedded System Design

在当今的工业世界中，嵌入式系统技术在安全关键应用中承担着越来越多的任务。自动驾驶就是一个突出的例子。因此，对功能安全的要求已成为一个关键问题，并定义了一项新技术的经济运行点。与此同时，由于新的微电子制造技术，新的硬件设备正在出现，这些设备固有地比以前的设备对故障更敏感。这导致可靠性大大降低，并要求进一步改进差错保护方法。然而，任何试图覆盖系统可能在其中使用的所有理论上可能的场景的所有错误的尝试都很容易导致过高的成本。测试社区内部的共识是，需要新的依赖于应用程序的方法来应对这些挑战。这意味着测试和容错策略必须只针对那些可能对实际使用硬件的应用程序产生影响的错误。这些应用程序由软件定义。拟议的项目追求的目标是开发一种硬件/软件跨层方法，以在软件级别评估硬件故障的影响。拟议分析的重点将放在低级软件上。将研究允许在执行系统软件时跟踪硬件故障传播的正式分析的方法。我们研究的一个特定目标是提供一种技术和工具来识别对软件或选定的可能安全关键的软件组件没有任何影响的硬件故障。此外，设想的方法将使我们能够根据故障影响对故障进行分类。例如，可以识别可能影响程序数据的故障，但可以保证这些故障不会改变程序的控制流程。与以前基于仿真的方法相比，它可以证明某些故障根本不影响系统行为，或者影响仅限于某些子功能。在评估系统的安全性和采取可能的故障保护措施时，这些信息非常有价值。该项目将首次展示所提议的分析的有用性，将其应用于设计提高系统故障恢复能力的措施。

Throughout today's industrial world Embedded System technology is taking over more and more tasks in safety-critical applications. Autonomous driving is a prominent example. As a result, the requirement of functional safety has become a key concern and, not rarely, defines the economic operating point of a new technology. At the same time, as a result of new microelectronic fabrication technologies, new hardware devices are emerging which suffer from an intrinsically higher susceptibility to faults than previous devices. This leads to a substantially lower degree of reliability and demands further improvements of methods for error protection. However, any attempt to cover all errors for all theoretically possible scenarios that a system might be used in can easily lead to excessive costs. There is consensus within the testing community that new application-dependent approaches are needed to meet these challenges. This means that strategies for test and error resilience must target only those errors that can really have an effect in the applications in which the hardware is actually used. These applications are defined by the software. The proposed project pursues the goal of developing a HW/SW cross-layer approach to assess the effect of hardware faults at the software level. The focus of the proposed analysis will lie on low-level software. Methods will be researched that allow for a formal analysis tracing the propagation of hardware faults when executing the system's software. A particular goal of our research is to provide techniques and a tool to identify hardware faults that do not have any effect on the software or on selected, possibly safety-critical, software components. Moreover, the envisioned approach will allow us to classify faults with respect to their fault effects. For example, faults can be identified that may affect the data of a program but it is guaranteed that they do not change its control flow.The proposed approach does not only give hints on what faults are particularly critical. In contrast to previous simulation-based approaches it can certify that certain faults do not affect the system behavior at all, or that the effect is limited to certain sub-functions. This information is highly valuable when evaluating the safety of a system and when taking possible measures for fault protection. The project will give a first demonstration for the usefulness of the proposed analysis by applying it to design measures that improve the fault resilience of the system.