Development of an Integrated Analog-Digital CAD System

本研究项目的目的是开发一个集成的模数CAD系统，该系统支持模拟和混合模数LSIS的电路和版图设计。该项目的成果总结如下：1.我们开发了一个象征性的布局系统。该系统允许设计者定义根据他的需要定制的任何设备的新布局图案。新建立的压缩算法使系统能够在对称约束下压缩模拟版图。我们开发了一个模块生成器开发系统。设计了一种从图形设计的布局中生成布局描述的方法。使用该系统，设计人员可以使用图形编辑器开发模块生成器，这比传统的编程更加人性化。我们已经建立了一种构建块和模拟元件的自动放置方法。布局算法是一种从所有可能的布局中寻找最优解的分支定界搜索算法。我们研制了一套用于CMOS型运算放大器的自动设计系统-AMPS。一个基于知识的过程，然后是数值优化，在一个巨大的解空间中有效地寻找一个好的设计。在器件大小调整过程中，版图信息被反向标注为“动态”，从而精确地考虑了版图寄生的影响，从而优化了电路性能。我们开发了版图驱动的逻辑综合系统。在逻辑重构过程中考虑了逻辑门的端子位置，这将减少最终电路的互连长度。该系统的输出是标准的单元布局。我们考虑了一种评估CAD工具的方法，并提出了一套全面的基准，适用于任何设计级别的CAD工具。我们的进一步研究将包括对LSI的验证和测试。

The purpose of this research project is the development of an integrated Analog-Digital CAD system that supports circuit and layout design for Analog and mixed Analog-Digital LSIS. The results of the project are summarized as follows.1. We have developed a symbolic layout system. The system allows a designer to define new layout patterns of any devices which are tailored according to his need. Newly established compaction algorithm enables the system to compact Analog layout under symmetry constraints.2. We have developed a system for module generator development. A method for generating layout description from a graphically designed layout has been devised. With the use of the system, a designer can develop a module generator using a graphic editor, which is more user-friendly than conventional programming.3. We have established an automatic placement method for building blocks and analog components. The placement algorithm is a branch-and-bound search for an optimal solution from all the possible placements.4. We have developed an automatic design system for CMOS operational amplifier-amps. A knowledge-based process followed by a numerical optimization searches for a good design effectively in a vast solution space. During device sizing, layout information are back-annotated "on the fly", thus circuit performance is optimized considering the effect of layout parasitics precisely.5. We have developed a layout-driven logic synthesis system. Terminal positions of logic gates are taken into account in a logic restructuring process, which consideration will reduce interconnection length of a final circuit. The output of the system is a standard cell layout.6. We have considered a method of evaluation for CAD tools, and proposed a comprehensive set of benchmarks which is applicable to CAD tools for any design levels.In this project we mainly focused on a synthesis phase of LSI design. Our further research will include verification and test of LSIs.