Optimizing Memory for Advanced Driver Assistance Systems and Autonomous Driving

由自定义加速器内核增强的异构多核架构如今广泛应用于许多嵌入式应用程序中。这些类型的计算平台最初是为消费应用开发的，现在正在进入安全关键应用领域，特别是在自动驾驶目前正在颠覆传统汽车电子开发的汽车领域。这种架构的巨大计算能力带来了进一步的巨大挑战。异构多核架构的速度与访问主存储器的速度之间的差距越来越大，造成了严重的限制。主存储器的主要类型是动态随机存取存储器（dram），它提供了存储密度和访问时间之间的最佳权衡。汽车先进驾驶辅助系统（ADAS）和自动驾驶（AD）的算法需要低延迟和巨大的外部存储带宽。因此，内存带宽成为最大的瓶颈之一。dram是为每个存储位的最低成本而优化的商品设备。因此，DRAM封装必须便宜，这限制了可用封装引脚。此外，dram具有复杂的内部架构和先进的内部预取，以弥合外部可用内存带宽和内部延迟之间的差距。DRAM技术表现出很大的参数变化（速度排序），存储单元必须刷新，这对温度非常敏感。这些特性使得在安全关键应用中使用dram非常具有挑战性。近年来出现了许多新的DRAM存储器件（如DDR4、LPDDR4、GDDR6、Wide I/O、HMB2）。目前尚不清楚这些内存模块将如何使用，以及它们在汽车环境中在带宽、延迟、功耗、温度、可靠性、安全性方面的表现如何。迄今为止，科学的DRAM研究主要集中在移动设备和数据中心。与安全关键的汽车领域相比，这些应用具有完全不同的概况。因此，考虑到汽车应用需求，迫切需要通过将基础研究转移到工业来缩小这一研究差距。据我们所知，目前还没有针对未来汽车应用优化DRAM内存子系统的调查或出版物。因此，在这个三方转移项目中，凯泽斯劳滕工业大学在DRAM建模、优化、控制器等方面的基础研究成果将进一步向汽车工业的适用性发展。弗劳恩霍夫IESE将以其在汽车和嵌入式系统安全方面的强大背景支持和协调这一转移。作为主要汽车供应商之一的应用合作伙伴，博世将从行业角度提供详细的应用技术、要求和具体的研究挑战。

Heterogeneous multi-core architectures enhanced by custom accelerator cores are today widely used in many embedded applications. These types of compute platforms that were originally developed for consumer applications are now entering safety critical applications, especially in the automotive domain where autonomous driving is currently disrupting the conventional automotive electronics development. The immense computing power of such architectures brings further large challenges. The increasing gap between speed of the heterogeneous multi-core architectures and accesses to the main memories poses a severe limit. The dominant type of main memories are Dynamic Random Access Memories (DRAMs) that offer the best trade-off between storage density and access times. Algorithms for Advanced Driver Assistance Systems (ADAS) and Autonomous Driving (AD) in automotive require low latency and huge external memory bandwidth. Thus, the memory bandwidth becomes one of the big bottlenecks. DRAMs are commodity devices optimized for minimum cost per storage bit. Hence, the DRAM package has to be cheap that limits the available package pins. Furthermore, DRAMs have a complex internal architecture with advanced internal prefetching to bridge the gap between external available memory bandwidth and internal latency. DRAM technologies exhibit a large parameter variation (speed sorting) and the storage cells have to be refreshed, which are very sensitive to temperature. These features make it very challenging to use DRAMs in safety critical applications. In recent years many new DRAM memory devices have been presented (e.g. DDR4, LPDDR4, GDDR6, Wide I/O, HMB2). It is not yet clear how these memory modules have to be used and how they will perform in the automotive context with respect to bandwidth, latency, power, temperature, reliability, safety and security. The scientific DRAM research so far mainly focused on mobile devices and data centers. These applications have totally different profiles compared to the safety critical automotive domain. Thus, there is a high need to close this research gap by transferring basic research to industry, taking the automotive application requirements into account. To the best of our knowledge, there are no investigations or publications that optimize the DRAM memory subsystem with respect to future automotive applications. Therefore, in this trilateral transfer project, the results gained from the basic research at TU Kaiserslautern about DRAM modelling, optimization, controllers etc. will be further developed towards applicability for automotive industry. The Fraunhofer IESE will support and coordinate this transfer with their strong background in safety for automotive and embedded systems. The application partner Bosch, one of the major automotive suppliers, will provide detailed application know-how, requirements and concrete research challenges from an industry perspective.