Design of efficient, dependable VLSI architectures based on a cross-layer-reliability approach using wireless communication as application

CMOS技术的不断缩小威胁着未来嵌入式系统的芯片可靠性。用最坏情况的方法和低级技术来确保可靠的硬件组件将不再可行。探索从微体系结构到应用程序（跨层设计）的多个层的知识变得势在必行。该建议的目标是开发一种方法，通过利用系统性能，硬件可靠性和实现复杂性的相互权衡来设计可靠的系统。以无线通信为例，说明了该方法的应用。将在以下领域进行科学研究：通过利用算法的错误鲁棒性，研究轻量级、自适应、内置的错误恢复技术;通过利用当前系统状态和运行时不断变化的服务质量要求，探索构件和系统一级的错误恢复之间的相互关系;开发在运行时在优化空间的三维中操作的控制器范例，即，系统性能、可靠性和能源效率。我们预期方法的总体目标是最大限度地减少面积方面的开销，尤其是能耗。这是通过只从对系统输出有重大影响的错误中恢复，并通过选择错误处理导致开销最小的层来实现的。

Continued progressive downscaling of CMOS technologies threatens the chip reliability of future embedded systems. Ensuring reliable hardware components with worst case methods and low level techniques will no longer be feasible. Exploring knowledge of multiple layers from micro-architecture to application (cross-layer design) becomes mandatory. This proposal targets the development of a methodology for designing dependable systems by exploiting the mutual trade-offs of system performance, hardware reliability and implementation complexity. Wireless communication is selected as application example for this approach. Scientific research will be carried out in the following fields: investigation of lightweight, adaptive, built-in error-resilience techniques by exploiting algorithmic error robustness; exploration of the interrelation between error resilience on building block and on system level by exploiting the current system state and at runtime-changing quality-of-service requirements; development of a controller paradigm operating in the three dimensions of the optimization space at runtime, i.e., system performance, reliability, and energy efficiency. The overall goal of our intended approach is to minimize the overhead in terms of area and especially energy consumption. This is achieved by recovering only from errors that have a significant impact on the system output and by choosing the layer in which the treatment of the error results in the least overhead.