Design of efficient, dependable VLSI architectures based on a cross-layer-reliability approach using wireless communication as application

CMOS技术的持续缩小威胁着未来嵌入式系统的芯片可靠性。使用最坏情况方法和低级技术确保可靠的硬件组件将不再可行。探索从微体系结构到应用程序（跨层设计）的多层知识变得必不可少。本提案的目标是开发一种设计可靠系统的方法，通过利用系统性能、硬件可靠性和实现复杂性之间的相互权衡。以无线通信为应用实例。科学研究将在以下领域开展：通过利用算法错误鲁棒性来研究轻量级，自适应，内置的错误恢复技术；通过利用当前系统状态和运行时变化的服务质量需求，探索构建块和系统级错误弹性之间的相互关系；开发在运行时优化空间的三个维度中运行的控制器范例，即系统性能，可靠性和能源效率。我们设计方法的总体目标是最小化面积开销，尤其是能耗。这是通过只从对系统输出有重大影响的错误中恢复，并通过选择错误处理导致最少开销的层来实现的。

Continued progressive downscaling of CMOS technologies threatens the chip reliability of future embedded systems. Ensuring reliable hardware components with worst case methods and low level techniques will no longer be feasible. Exploring knowledge of multiple layers from micro-architecture to application (cross-layer design) becomes mandatory. This proposal targets the development of a methodology for designing dependable systems by exploiting the mutual trade-offs of system performance, hardware reliability and implementation complexity. Wireless communication is selected as application example for this approach. Scientific research will be carried out in the following fields: investigation of lightweight, adaptive, built-in error-resilience techniques by exploiting algorithmic error robustness; exploration of the interrelation between error resilience on building block and on system level by exploiting the current system state and at runtime-changing quality-of-service requirements; development of a controller paradigm operating in the three dimensions of the optimization space at runtime, i.e., system performance, reliability, and energy efficiency. The overall goal of our intended approach is to minimize the overhead in terms of area and especially energy consumption. This is achieved by recovering only from errors that have a significant impact on the system output and by choosing the layer in which the treatment of the error results in the least overhead.