Design of efficient 3D integrated DRAM subsystem architectures based on detailed designspace explorations and modeling

基于详细设计空间探索和建模的高效 3D 集成 DRAM 子系统架构设计

基本信息

批准号：
248750294
负责人：
Professor Dr.-Ing. Norbert Wehn
金额：
--
依托单位：
Lehrstuhl Entwurf Mikroelektronischer Systeme
依托单位国家：
德国
项目类别：
Research Grants
财政年份：
2013
资助国家：
德国
起止时间：
2012-12-31 至 2018-12-31
项目状态：
已结题

来源：
https://gepris.dfg.de/gepris/projekt/248750294?language=en
关键词：
Design efficient 3D integrated DRAM

项目摘要

The progress in the field of 3D integration of microelectronic systems enables a dependable and costeffective density increase of ICs in a single package. The possibility to closely integrateheterogeneous ICs with different technologies and functionalities opens a way out of the"Memory/Processor Gap" via integration of scalable 3D integrated DRAMs with very highcommunication bandwidths and the corresponding logic (e.g. memory controller). In this way 3Dintegration of standard DRAMs with MPSoCs can largely improve the energy efficiency and increasethe memory bandwidth. However, this is only the starting point for a complete revision of the memorysubsystem of MPSoCs considering the new possibilities of 3D integration. I.e. DRAM architectures,their interfaces and memory controllers have to be thoroughly reinvestigated to achieve higherbandwidth, better energy efficiency, lower system latency, higher memory packing density and largerscalability compared to the state-of-the-art architectures. However, the design space for such a 3D-DRAMsubsystem is very large, since it covers the 3D-DRAM cube, the interfaces and the memorycontroller. This design space has to be systematically explored with appropriate metrics to obtain theoptimum configuration parameters. To the best of our knowledge there are no investigations orpublications to optimize 3D-DRAM, interfaces and controller jointly. Hence, the objective for thisproposal is the co-optimization of memory controller, interfaces and 3D-DRAM cube especially tomobile computing constraints and requirements.

微电子系统3D集成领域的进展使一个包装中IC的可靠密度增加。通过与可扩展的3D积分DRAM的集成，具有非常高的通信带宽和相应的逻辑（例如，内存控制器），与不同技术和功能紧密整合IC的可能性通过“内存/处理器差距”开辟了道路。以这种方式，使用MPSOC的标准DRAM的3DINTEMERATION可以在很大程度上提高能源效率并提高记忆带宽。但是，这只是考虑到3D集成的新可能性的MPSOC的内存存储系统的完整修订的起点。 IE。与最先进的体系结构相比，必须对DRAM体系结构，其接口和存储器控制器进行彻底重新测试，以实现更高的带宽，更好的能源效率，较低的系统延迟，更高的存储器堆积密度和大量计算。但是，此类3D-DRAMSUBSYSTEM的设计空间非常大，因为它涵盖了3D-DRAM Cube，接口和内存controller。必须使用适当的指标系统地探索此设计空间，以获得theoptimus配置参数。据我们所知，没有任何调查或共同优化3D-DRAM，界面和控制器的研究。因此，此处的目的是对内存控制器，界面和3D-DRAM立方体的合作化，尤其是Tomobile计算的限制和要求。