Design of efficient 3D integrated DRAM subsystem architectures based on detailed designspace explorations and modeling

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The progress in the field of 3D integration of microelectronic systems enables a dependable and costeffective density increase of ICs in a single package. The possibility to closely integrateheterogeneous ICs with different technologies and functionalities opens a way out of the"Memory/Processor Gap" via integration of scalable 3D integrated DRAMs with very highcommunication bandwidths and the corresponding logic (e.g. memory controller). In this way 3Dintegration of standard DRAMs with MPSoCs can largely improve the energy efficiency and increasethe memory bandwidth. However, this is only the starting point for a complete revision of the memorysubsystem of MPSoCs considering the new possibilities of 3D integration. I.e. DRAM architectures,their interfaces and memory controllers have to be thoroughly reinvestigated to achieve higherbandwidth, better energy efficiency, lower system latency, higher memory packing density and largerscalability compared to the state-of-the-art architectures. However, the design space for such a 3D-DRAMsubsystem is very large, since it covers the 3D-DRAM cube, the interfaces and the memorycontroller. This design space has to be systematically explored with appropriate metrics to obtain theoptimum configuration parameters. To the best of our knowledge there are no investigations orpublications to optimize 3D-DRAM, interfaces and controller jointly. Hence, the objective for thisproposal is the co-optimization of memory controller, interfaces and 3D-DRAM cube especially tomobile computing constraints and requirements.