Studies on Functional Memory Type Parallel Processor Architectures and Their Massively Parallel Algorithms.

本文对一种并行处理器结构--功能存储器型并行处理器结构（FunctionalMemoryTypeParallelProcessorArchitecture，FMPP）及其上的大规模并行算法进行了深入的研究。结果总结如下。(1)FMPP的大规模并行计算能力研究：在存储器电路中引入一定的计算能力，使FMPP能够在存储器电路中实现高度并行计算。(2)FMPP集成电路技术的研究：基于最近的CAM LSI的技术趋势，这是FMPP的主要组成部分，在0.8妈妈CMOS技术的CAM LSI的集成规模预测为100 Kbit的SRAM单元和400 Kbit的DRAM单元。在0.5 μ m工艺下，它将达到1 Mbit的DRAM单元。（3）一种新的FMPP结构的研究：提出了一种新的FMPP结构，称为位并行块并行（BPBP）FMPP。到目前为止，基于CAM的位串行字并行（BSWP）实现被认为是最有前途的FMPP结构之一。BSWP FMPP在合理的硬件数量下实现了大规模并行计算。然而，它不允许两个字之间的操作，这限制了BSWP FMPP的适用性。BBP设计用于对两个字执行逻辑和算术运算。这些操作同时在称为块的每组字上执行。因此，BPBPFMPP在保持BSWP的高集成密度的同时实现了高性能，并且适合于各种应用。(4)FMPP大规模并行算法的研究：我们已经开发了各种并行算法的FMPP具有高度并行的SIMD计算方案。算法的目标包括模式匹配、最短路径问题、逻辑模拟、直线求交、光线跟踪和神经网络模拟。

We have made an in-depth study on a parallel processor architecture called FMPP (Functional Memory Type Parallel Processor Architecture) and massively parallel algorithms on FMPP. Results are summarized as follows.(1) Studies on Massively Parallel Computation Capability of FMPP: Introduction of some computational power inside memory circuits enables FMPP to realize a highly parallel computation in the memory circuits.(2) Studies on Integrated Circuit Technology for FMPP: Based on the recent technology trend of a CAM LSI which is the principal component of FMPP, Integration scale of CAM LSIs in 0.8 mum CMOS technology is predicted to be 100 Kbit with SRAM cells and 400 Kbit with DRAM cells. In 0.5 mum technology, it will reach 1 Mbit with DRAM cells(3) Studies on a new FMPP architecture: A new architecture of FMPP called bit-parallel block-parallel (BPBP) FMPP has been proposed. So far, a bit-serial word-parallel (BSWP) implementation based on a CAM is mainly considered as one of promising architectures of FMPP. The BSWP FMPP achieves massively parallel computation in a reasonable hardware amount. It however does not allow operations between two words, which restriction limits the the applicability of the BSWP FMPP. The BPBP is designed to execute logical and arithmetic operations on two words. These operations are performed simultaneously on every group of words call a block. BPBP FMPP hereby achieves a high performance while maintaining high integration density of the BSWP, and in suitable for various applications.(4) Studies on massively parallel algorithms for FMPP: We have developed various parallel algorithms for FMPP which has a highly parallel SIMD computation scheme. The targets of the algorithms include pattern matching, the shortest path problem, logic simulation, intersection calculation of lines, ray tracing, and neural network simulation.